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w WM9715L ac?97 audio and touchpanel codec wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ production data, december 2007, rev 4.0 copyright ? 2007 wolfson microelectronics plc. description the WM9715L is a highly integrated input / output device designed for mobile computing and communications. the device can connect directly to a 4-wire or 5-wire touchpanel, mono or stereo microphones, stereo headphones and a mono speaker, reducing total component count in the system. additionally, phone input and output pins are provided for seamless integration with wireless communication devices. the WM9715L also offers up to four auxiliary adc inputs for analogue measurements such as temperature or light. to monitor the battery voltage in portable systems, the WM9715L has two uncommitted comparator inputs. all device functions are accessed and controlled through a single ac-link interface compatible with the ac?97 standard (rev 2.2). additionally, the WM9715L can generate interrupts to indicate pen down, pen up, availability of touchpanel data, low battery, and dead battery. the WM9715L operates at supply voltages from 1.8 to 3.6 volts. each section of the chip can be powered down under software control to save power. the device is available in a small leadless 7x7mm qfn package, ideal for use in hand- held portable systems. features ? ac?97 rev 2.2 compatible stereo codec - dac snr 90db, thd ?86db - adc snr 88db, thd ?88db - variable rate audio, supports all wince sample rates - tone control, bass boost and 3d enhancement ? on-chip 45mw headphone driver ? on-chip 400mw mono speaker driver ? stereo, mono or differential microphone input - automatic level control (alc) ? auxiliary mono dac (ring tone or dc level generation) ? seamless interface to wireless chipset ? resistive touchpanel interface - supports 4-wire and 5-wire panels - 12-bit resolution, inl 3 lsbs (<0.5 pixels) - x, y and touch-pressure (z) measurement - pen-down detection supported in sleep mode ? 2 comparator inputs for battery monitoring ? up to 4 auxiliary adc inputs ? 1.8v to 3.6v supplies ? 7x7mm qfn applications ? personal digital assistants (pda) ? smartphones ? handheld and tablet computers block diagram sdatain sync bitclk resetb sdataout genirq y+/tr x+/br wiper/ aux4 x-/tl y-/bl xtlin xtlout spdif_out tpgnd tpvdd adcirq pendown
WM9715L production data w pd rev 4.0 december 2007 2 table of contents description .......................................................................................................1 features.............................................................................................................1 applications .....................................................................................................1 block diagram .................................................................................................1 table of contents .........................................................................................2 pin configuration...........................................................................................4 ordering information ..................................................................................4 pin description ................................................................................................5 absolute maximum ratings.........................................................................6 recommended operating conditions .....................................................6 electrical characteristics ......................................................................7 audio outputs.......................................................................................................... 7 audio inputs.............................................................................................................. 8 auxiliary mono dac (auxdac).............................................................................. 8 touchpanel and auxiliary adc .......................................................................... 9 comparators ........................................................................................................... 9 reference voltages ........................................................................................... 10 digital interface characteristics................................................................ 10 headphone / speaker output thd versus power ..................................... 11 power consumption............................................................................................ 12 device description .......................................................................................13 introduction.......................................................................................................... 13 audio paths overview......................................................................................... 14 audio inputs ....................................................................................................15 line input ................................................................................................................. 15 microphone input................................................................................................. 15 phone input............................................................................................................. 17 pcbeep input ........................................................................................................... 18 audio adc..........................................................................................................19 record selector ................................................................................................. 20 record gain............................................................................................................ 21 automatic level control.................................................................................. 22 audio dacs .......................................................................................................25 stereo dac.............................................................................................................. 25 auxiliary dac.......................................................................................................... 28 analogue audio outputs ...........................................................................30 headphone outputs ? hpoutl and hpoutr.................................................. 30 ear speaker output ? out3............................................................................... 31 loudspeaker outputs ? lout2 and rout2.................................................... 32 phone output (monoout)................................................................................... 33 thermal sensor .................................................................................................... 33 digital audio (spdif) output ............................................................................. 34 audio mixers ........................................................................................................... 35 variable rate audio / sample rate conversion ...............................37
production data WM9715L w pd rev 4.0 december 2007 3 touchpanel interface................................................................................38 principle of operation - four-wire touchpanel ..................................... 38 principle of operation - five-wire touchpanel.... .................................... 40 controlling the touchpanel digitiser ....................................................... 42 auxiliary adc inputs ....................................................................................47 battery measurement using the bmon/aux3 pin ....................................... 47 battery alarm and analogue comparators ....................................48 interrupt control.......................................................................................51 the adcirq pin ........................................................................................................ 51 the pendown pin ................................................................................................... 51 the genirq pin........................................................................................................ 51 power management .....................................................................................54 unused analogue inputs and outputs ......................................................... 57 ac97 data and control interface .........................................................58 interface protocol............................................................................................ 58 interface timing ................................................................................................... 59 register map...................................................................................................62 register bits by address .................................................................................. 63 applications information .........................................................................72 recommended external components........................................................... 72 recommended components values ............................................................... 73 line output ............................................................................................................. 73 ac-coupled headphone output....................................................................... 74 dc coupled (capless) headphone output ................................................... 74 btl loudspeaker output ................................................................................... 75 combined stereo headset / btl ear speaker ............................................. 75 combined headset / single-ended ear speaker......................................... 75 package dimensions ....................................................................................76 important notice ..........................................................................................77 address:................................................................................................................... 77
WM9715L production data w pd rev 4.0 december 2007 4 pin configuration ordering information device temp. range package moisture level sensitivity peak soldering temp WM9715Lgefl/v -25 to +85 o c 48-lead qfn (pb-free) msl3 260 o c WM9715Lgefl/rv -25 to +85 o c 48-lead qfn (pb-free, tape and reel) msl3 260 o c note: reel quantity = 2,200
production data WM9715L w pd rev 4.0 december 2007 5 pin description pin name type description 1 dbvdd supply digital i/o buffer supply 2 xtlin digital input clock crystal connection 1 / external clock input 3 xtlout digital output clock crystal connection 2 4 dgnd1 supply digital ground (return path for both dcvdd and dbvdd) 5 sdataout digital input serial data output from controller / input to WM9715L 6 bitclk digital output serial interface clock output to controller 7 dgnd2 supply digital ground (return path for both dcvdd and dbvdd) 8 sdatain digital output serial data input to controller / output from WM9715L 9 dcvdd supply digital core supply 10 sync digital input serial interface synchronisation pulse from controller 11 resetb digital input reset (asynchronous, active low, resets all registers to their default) 12 wiper / aux4 analogue input top sheet connection for 5-wire touchpanels / auxiliary adc input 13 tpvdd supply touchpanel driver supply 14 x+/br analogue input touchpanel connection: x+ (right) for 4-wire / bottom right for 5-wire 15 y+/tr analogue input touchpanel connection: y+ (top) for 4-wire / top right for 5-wire 16 x-/tl analogue input touchpanel connection: x- (left) for 4-wire / top left for 5-wire 17 y-/bl analogue input touchpanel connection: y- (bottom) for 4-wire / bottom left for 5-wire 18 tpgnd supply touchpanel driver ground 19 pcbeep anal ogue input line input to analogue audio mixers, typically used for beeps 20 phone analogue input phone input (rx) 21 mic1 analogue input left microphone or microphone 1 input 22 mic2 analogue input right microphone or microphone 2 input 23 lineinl analogue input left line input 24 lineinr analogue input right line input 25 avdd supply analogue supply (feeds audio dacs, adcs, pgas, mic boost, mixers) 26 agnd supply analogue ground 27 vref analogue output internal reference voltage (buffered cap2) 28 micbias analogue output bias voltage for microphones (buffered cap2 1.8) 29 comp1 / aux1 analogue input comparator 1 (dead battery alarm) / auxiliary adc input 1 30 comp2 / aux2 analogue input comparator 2 (low battery alarm) / auxiliary adc input 2 31 bmon / aux3 analogue input battery monitor input / auxiliary adc input 3 32 cap2 analogue in / out internal reference voltage (normally avdd/2, if not overdriven) 33 monoout analogue output mono output, intended for phone tx signal 34 spkgnd supply speaker ground (feeds output buffers on pins 35 and 36) 35 lout2 analogue output left output 2 (speaker, line or headphone) 36 rout2 analogue output right output 2 (speaker, line or headphone) 37 out3 analogue output analogue output 3 (from auxdac or headphone pseudo-ground) 38 spkvdd s upply speaker supply (feeds output buffers on pins 35 and 36) 39 hpoutl analogue output headphone left output 40 hpgnd supply headphone ground (feeds output buffers on pins 37, 39, 41) 41 hpoutr analogue output headphone right output 42 agnd2 supply analogue ground, chip substrate 43 hpvdd supply headphone supply (feeds output buffers on pins 37, 39, 41) 44 dnc do not connect leave this pin unconnected 45 genirq digital in / out general irq (interrupt request) output 46 pendown digital output indicates that screen is being touched 47 adcirq digital in / out auxadc ?data ready? interrupt; also determines power up status. (see ?power management? and ?applications? sections) 48 spdif_out digital in / out spdif digital audio output note: it is recommended that the qfn ground paddle should be connected to analogue ground on the application pcb.
WM9715L production data w pd rev 4.0 december 2007 6 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max digital supply voltages (dcvdd, dbvdd) -0.3v +3.63v analogue supply voltages (avdd, hpvdd, spkvdd, tpvdd) -0.3v +3.63v touchpanel supply voltage (tpvdd) avdd -0.3v avdd +0.3v voltage range digital inputs dgnd -0.3v dbvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v voltage range touchpanel inputs x+, x-, y+ and y- tpvdd +0.3v voltage range touchpanel inputs x+, x-, y+ and y- avdd +0.3v voltage range, bmon/aux3 (pin31) +5v operating temperature range, t a -25 o c +85 o c recommended operating conditions parameter symbol test conditions min typ max unit digital input/output buffer supply range dbvdd notes 1, 2 1.8 3.6 or avdd+0.3 v digital core supply range dcvdd notes 1, 2 1.8 3.6 or avdd+0.3 v analogue supply range avdd, hpvdd, spkvdd, tpvdd 1.8 3.6 v digital ground dcgnd, dbgnd 0 v analogue ground agnd, hpgnd, spkgnd, tpgnd 0 v difference agnd to dgnd note 3 -0.3 0 +0.3 v notes: 1. avdd, dcvdd and dbvdd can all be different 2. digital supplies (dcvdd, dbvdd) must not exceed analogue supplies (avdd, hpvdd, s pkvdd, tpvdd) by more than 0.3v 3. agnd is normally the same as dgnd 4. dcvdd must be lower than or equal to dbvdd
production data WM9715L w pd rev 4.0 december 2007 7 electrical characteristics audio outputs test conditions dbvdd=3.3v, dcvdd = 3.3v, avdd=hpvdd=spkvdd =3.3v, t a = +25 o c, 1khz signal, fs = 48khz, 18-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit dac to line-out (l/rout2 with 10k ? load) full-scale output avdd = 3.3v, pga gains set to 0db 1 v rms signal to noise ratio (a-weighted) snr 85 90 db total harmonic distortion + noise thd+n -3db output -86 -80 db power supply rejection psrr 100mv, 20hz to 20khz signal on avdd 50 db speaker output (lout2/rout2 with 8 ? bridge tied load, inv=1) output power p o output power is very closely correlated with thd; see below. output power at 1% thd p o 400 mw abs. max output power p o max 500 mw total harmonic distortion thd p o =150mw -65 0.05 db % signal to noise ratio (a-weighted) snr 90 97 db headphone output (hpoutl/r with 16 ? or 32 ? load) output power per channel p o output power is very closely correlated with thd; see below. p o =10mw, r l =16 ? -80 p o =10mw, r l =32 ? -81 p o =20mw, r l =16 ? -77 -70 total harmonic distortion (note 1) thd p o =20mw, r l =32 ? -79 db signal to noise ratio (a-weighted) snr 90 95 db note: 1. all thd values are valid for the output power level quoted above ? for example, at hpvdd=3.3v and r l =16 ? , thd is ?80db when output power is 10mw. higher output power is possible, but will result in deterioration in thd.
WM9715L production data w pd rev 4.0 december 2007 8 audio inputs test conditions dbvdd=3.3v, dcvdd = 3.3v, avdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, 18-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit lineinl/r, micl/r and phone pins avdd = 3.3v 1.0 avdd = 1.8v 0.545 full scale input signal level (for adc 0db input at 0db gain) v infs differential input mode (ms = 01) half of the value listed above v rms phone, lineinl/r pins pga gain 10 17 22 input resistance r in mic1/2 pins pga gain 6 12 18 k ? input capacitance 5 pf line input to adc (lineinl, lineinr) signal to noise ratio (a-weighted) snr 80 88 db total harmonic distortion thd -6dbfs -88 -80 db power supply rejection psrr 20hz to 20khz 50 db microphone input to 32 ? btl ear speaker on out3/hpoutl signal to noise ratio (a-weighted) snr 80 db total harmonic distortion thd -80 db power supply rejection ratio psrr 50 db auxiliary mono dac (auxdac) test conditions avdd = 3.3v, t a = +25 o c, unless otherwise stated. parameter symbol test conditions min typ max unit resolution 12 bits full scale output voltage avdd=3.3v 1 vrms signal to noise ratio (a-weighted) snr 65 70 db total harmonic distortion thd -63 -50 db
production data WM9715L w pd rev 4.0 december 2007 9 touchpanel and auxiliary adc test conditions dbvdd=3.3v, dcvdd = 3.3v, avdd = tpvdd = 3.3v, t a = +25 o c, mclk = 24.576 mhz, unless otherwise stated. parameter symbol test conditions min typ max unit input pins x+, x-, y+, y-, wiper/aux4, comp1/aux1, comp2/aux2 and bmon/aux3 input voltage agnd avdd v input leakage current aux pin not selected as aux adc input <10 na adc resolution 12 bits differential non-linearity error dnl -0.99 0.15 +1.75 lsb integral non-linearity error inl 3 lsb offset error 4 lsb gain error 8 lsb power supply rejection psrr 50 db switch matrix resistance 10 ? programmable pull-up resistor r pu rpu = 000001 63 68 73 k ? pen down detector threshold vdd/2 v pil = 1 400 pressure measurement current i p pil = 0 200 a bmon/aux3 (pin 31 only) avdd = 3.3v agnd 5 v input range avdd = 1.8v agnd 3.3 v scaling -3% 1/3 +3% during measurement 30 input resistance (note 1) average over time 30 / duty cycle k ? note: 1. current only flows into pin 31 during a measurement. at all other times, bmon/aux3 is effectively an open circuit. comparators test conditions avdd = 3.3v, t a = +25 o c, unless otherwise stated. parameter symbol test conditions min typ max unit comp1/aux1 and comp2/aux2 (pins 29, 30) input voltage agnd avdd v input leakage current pin not selected as aux adc input <10 na comparator input offset (comp1, comp2 only) -50 +50 mv comp2 delay (comp2 only) 24.576mhz crystal 0 10.9 s
WM9715L production data w pd rev 4.0 december 2007 10 reference voltages test conditions dbvdd=3.3v, dcvdd = 3.3v, avdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, 18-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit audio adcs, dacs, mixers reference input/output cap2 pin 1.6 1.65 1.7 v buffered reference output vref pin 1.6 1.65 1.7 v microphone bias bias voltage v micbias 2.88 2.97 3.06 v bias current source i micbias 3 ma output noise voltage vn 1k to 20khz 15 nv/ hz digital interface characteristics test conditions dbvdd = 3.3v, dcvdd = 3.3v, t a = +25 o c, unless otherwise stated. parameter symbol test conditions min typ max unit digital logic levels (all digital input or output pins) ? cmos levels input high level v ih dbvdd 0.7 v input low level v il dbvdd 0.3 v output high level v oh source current = 2ma dbvdd 0.9 output low level v ol sink current = 2ma dbvdd 0.1 clock frequency master clock (xtlin pin) 24.576 mhz ac?97 bit clock (bit_clk pin) 12.288 mhz ac?97 sync pulse (sync pin) 48 khz note: 1. all audio and non-audio sample rates and other timing scales proportionately with the master clock. 2. for signal timing on the ac-link, please refer to the ac?97 specification (revision 2.2)
production data WM9715L w pd rev 4.0 december 2007 11 headphone / speaker output thd versus power headphone power vs thd+n (32ohm load) -100 -80 -60 -40 -20 0 5 10 15 20 25 30 power (mw) thd+n (db) headphone power vs thd+n (16ohm load) -100 -80 -60 -40 -20 0 102030405060 power (mw) thd+n (db)
WM9715L production data w pd rev 4.0 december 2007 12 power consumption the power consumption of the WM9715L depends on the following factors. ? supply voltages: reducing the supply voltages also reduces digital supply currents, and therefore results in significant power savings especially in the digital sections of the WM9715L. ? operating mode: significant power savings can be achieved by always disabling parts of the WM9715L that are not used (e.g. audio adc, dac, touchpanel digitiser). mode description 26h 14:8 24h 15:0 other settings total power vi ( ma ) vi ( ma ) vi ( ma ) ( mw ) off (lowest possible power) 1111111 0111111111111111 58h, svd = 1 3.3 0.0005 3.3 0 3.3 0 0.00165 clocks stopped 2.5 0.0004 2.5 0 2.5 0 0.001 1.8 0.0003 1.8 0 1.8 0 0.00054 lps (low power standby) 1111111 0111111111111111 3.3 0.005 3.3 0 3.3 0 0.0165 vref maintained usin g 1mohm strin g 2.5 0.004 2.5 0 2.5 0 0.01 1.8 0.003 1.8 0 1.8 0 0.0054 standby mode (ready to playback) 1110111 0111111111111111 3.3 0.56 3.3 0 3.3 0 1.848 vref maintained using 50kohm string 2.5 0.37 2.5 0 2.5 0 0.925 1.8 0.241 1.8 0 1.8 0 0.4338 "idle" mode 1100111 0111111111111111 3.3 1.1 3.3 0 3.3 0 3.63 vref maintained using 50kohm string 2.5 0.76 2.5 0 2.5 0 1.9 use lps mode instead, if possible 1.8 0.508 1.8 0 1.8 0 0.9144 touchpanel only (waiting for pen-down) 1101111 0111111111111111 76h = 0c00h 3.3 0.05 3.3 1.301 3.3 3.26 15.2163 ac-link running 78h = 0001h 2.5 0.02 2.5 0.883 2.5 2.1 7.5075 1.8 0.009 1.8 0.571 1.8 1.41 3.582 touchpanel only (continuous conversion) 1001111 0111111111111111 76h = 0c00h 3.3 0.08 3.3 5.85 3.3 2.67 28.38 93.75 points per second 78h = c001h 2.5 0.04 2.5 3.922 2.5 2.1 15.155 1.8 0.027 1.8 2.87 1.8 1.41 7.7526 phone call - using headphone / ear speaker 0110011 0111100010101100 0eh, bit 7 = 1 3.3 2.36 3.3 0 3.3 0 7.788 hpoutl, hpoutr and out3 active (mic gain boost) 2.5 1.838 2.5 0 2.5 0 4.595 ac-link stopped 1.8 1.218 1.8 0 1.8 0 2.1924 phone call - using loudspeaker 1110011 0111101100110100 0eh, bit 7 = 1 3.3 2.385 3.3 0 3.3 0 7.8705 ac-link stopped (mic gain boost) 2.5 1.837 2.5 0 2.5 0 4.5925 1.8 1.218 1.8 0 1.8 0 2.1924 record from mono microphone 1000110 0110101111111111 0eh, bit 7 = 1 3.3 3.27 3.3 11.21 3.3 2.6 56.364 with micbias (mic gain boost) 2.5 2.66 2.5 7.78 2.5 2.13 31.425 all analogue outputs disabled 1.8 1.838 1.8 5.21 1.8 1.41 15.2244 record phone call 0000000 0000000010001000 0eh, bit 7 = 1 3.3 9.461 3.3 12.22 3.3 2.62 80.1933 both sides mixed to mono (mic gain boost) 2.5 7.46 2.5 8.552 2.5 2.1 45.28 call using headphone / ear speaker 1.8 5.318 1.8 5.799 1.8 1.48 22.6746 dac playback - using loudspeaker 1000001 0001111101110111 3.3 3.45 3.3 9.884 3.3 2.6 52.5822 2.5 2.549 2.5 6.755 2.5 2.1 28.51 1.8 1.738 1.8 4.606 1.8 1.41 13.9572 dac playback - using headphone 0000001 0001110011101111 3.3 3.62 3.3 9.8 3.3 2.6 52.866 2.5 2.71 2.5 6.78 2.5 2.1 28.975 1.8 1.748 1.8 4.606 1.8 1.47 14.0832 dac playback - to line-out 0000001 0001110011110111 3.3 3.62 3.3 9.8 3.3 2.6 52.866 2.5 2.71 2.5 6.78 2.5 2.1 28.975 1.8 1.748 1.8 4.606 1.8 1.41 13.9752 maximum power (everything on) 0000000 0000000000000000 0eh, bit 7 = 1 3.3 9.593 3.3 12.26 3.3 2.62 80.7609 (mic gain boost) 2.5 7.37 2.5 8.563 2.5 2.12 45.1325 1.8 5.388 1.8 5.8 1.8 1.48 22.8024 avdd dcvdd dbvdd table 1 supply current consumption notes: 1. all figures are at t a = +25 o c, audio sample rate fs = 48khz, with zero signal (quiescent). 2. the power dissipated in the headphone, speaker and touchpanel is not included in the above table.
production data WM9715L w pd rev 4.0 december 2007 13 device description introduction the WM9715L is designed to meet the mixed-signal requirements of portable and wireless computer systems. it includes audio recording and playback, touchpanel digitisation, battery monitoring, auxiliary adc and interrupt functions, all controlled through a single 5-wire ac-link interface. software support the basic audio features of the WM9715L are software compatible with standard ac?97 device drivers. however, to better support the touchpanel and other additional functions, wolfson microelectronics supplies custom device drivers for selected cpus and operating systems. please contact your local wolfson sales office for more information. ac?97 compatibility the WM9715L uses an ac?97 interface to communicate with a microprocessor or controller. the audio functions are largely compliant with ac?97 revision 2.2. the following differences from the ac?97 standard are noted: ? pinout: the function of some pins has been changed to support device specific features. the phone and pcbeep pins have been moved to different locations on the device package. ? package: the default package for the WM9715L is a 7 7mm leadless qfn package. audio mixing: the WM9715L handles all the audio functions of a smartphone, including audio playback, voice recording, phone calls, phone call recording, ring tones, as well as simultaneous use of these features. the ac?97 mixer architecture does not fully support this. the WM9715L therefore uses a modified ac?97 mixer architecture with three separate mixers. ? tone control, bass boost and 3d enhancement: these functions are implemented in the digital domain and therefore affect only signals being played through the audio dacs, not all output signals as stipulated in ac?97. some other functions are additional to ac?97: ? on-chip btl loudspeaker driver ? on-chip btl driver for ear speaker (phone receiver) ? auxiliary mono dac for ring tones, system alerts etc. ? touchpanel controller ? auxiliary adc inputs ? 2 analogue comparators for battery alarm ? programmable filter characteristics for tone control and 3d enhancement
WM9715L production data w pd rev 4.0 december 2007 14 audio paths overview linel pga l lout2 pin 35 monoout pin 33 r rout2 pin 36 out3 pin 37 liner micr dacr liner micr dacr phone pcbeep monomix phone pcbeep monomix micl micl alcl alcr alcl alcr left channel 18 bit adc variable slot 5c:1-0 (ass) 5c:3 (hpf) 5c:4 (adco) alc:5ch/60h/62h 12 bit resistor string dac 2eh/64h/12h:0(en) auxdac auxdac spkrmix spkrmix from linel pga from dacl to spkr mixer to spkr mixer left channel 18 bit dac 18h:12-8 00000 = +12db 11111 = -34.5db headphone mixer l 1 8 h : 1 5 1 0 h : 1 5 0 a h : 1 5 - 1 2 phone mixer 1 8 h : 1 3 0ah7:4 1 a h : 1 3 - 1 1 10h:12-8 00000 = +12db 11111 = -34.5db 0ch:0-4 00000 = +12db 11111 = -34.5db 0eh:12-8 00000 = +12db 11111 = -34.5db 1ah: 10-8 1ah:14 0 = 0db 1 = 20db 18h:4-0 00000 = +12db 11111 = -34.5db 10h:5-0 00000 = +12db 11111 = -34.5db 0eh:5-0 00000 = +12db 11111 = -34.5db headphone mixer r 0 a h : 1 5 - 1 2 speaker mixer 1 0 h : 1 4 1 8 h : 1 4 0ch:14 0 a h : 1 1 - 8 right channel 18 bit adc variable slot 5c:1-0 (ass) 5c:3 (hpf) 5c:4 (adco) 1ah: 2-0 zero- cross detect 02h:12-8 00000 = 0db 11111 = -46.5db zero- cross detect 04h:12-8 00000 = 0db 11111 = -46.5db hpoutl pin 39 zero- cross detect 06h:4-0 00000 = 0db 11111 = -46.5db zero- cross detect 16h:4-0 00000 = 0db 11111 = -46.5db zero- cross detect 04h:4-0 00000 = 0db 11111 = -46.5db hpoutr pin 41 zero- cross detect 02h:4-0 00000 = 0db 11111 = -46.5db 0db / 20db oeh:6-5 (ms) alc:5ch/60h/62h 0eh:6-5 (ms) 5ch:8 (ds) 02h:6 (inv) 02h:7 (zc) 02h:15 (mute) 04h:7 (zc) 04h:15 (mute) 06h:7 (zc) 06h:15 (mute) 16h:7 (zc) 16h:15 (mute) 04h:7 (zc) 04h:15 (mute) 02h:7 (zc) 02h:15 (mute) 16h:10-9 (out3src) 16h:8 (src) 1ah:14 0 = 0db 1 = 20db 1ch:6 (grr=1) 1ch:5-0 11111 = +30db 00000 = -17.25db 1ch:6 (grr=0) 1ch:3:0 0000 = 0db 1111 = +22.5db 1ch:6 (grl=1) 1ch:13-8 11111 = +30db 00000 = -17.25db 1ch:13 (grl=0) 1ch:11:8 0000 = 0db 1111 = +22.5db slot 3 tone and 3d 08h / 22h / 20h:13 (3de) slot 4 tone and 3d 08h / 22h / 20h:13 (3de) ac link ac link ac link pcm pga pcm pga adc pga adc pga phone pga micl pga liner pga micr pga right channel 18 bit dac l line volume r line volume l headphone volume r headphone volume mono volume out3 volume 500k 500k 50k 50k pr3 (ref disable) & 58h:10 (svd) 3.6k 4.5k 1 0 h : 1 3 0 c h : 1 5 0 c h : 1 5 6db -> -15db 6db -> -15db 6db -> -15db 6db -> -15db 6db -> -15db 1 8 h : 1 3 1 8 h : 1 5 1 8 h : 1 4 1 0 h : 1 3 1 0 h : 1 5 1 0 h 1 4 1 4 h : 1 5 - 1 2 0 e h : 1 3 + 7 1 4 h : 1 5 - 1 2 1 4 h : 1 1 - 7 1 4 h : 1 1 - 8 1 4 h : 1 1 - 7 1 4 h : 1 1 - 8 1 a h : 1 3 - 1 1 1 2 h : 1 5 - 1 2 1 2 h : 7 - 4 1 2 h : 1 5 - 1 2 1 2 h : 1 1 - 8 6db -> -15db 6db -> -15db 0db / 20db 6db -> -15db 6db -> -15db 6db -> -15db 6db -> -15db 0db / 20db 6db -> -15db 6db -> -15db 6db -> -15db 6db -> -15db 16h:8 (src) 1 0 1 0 1ch:15 (mute) gain ranges: gain ranges: 1ch:15 (mute) 14h:15-12 0 e h : 1 4 + 7 14h:15-12 1 0 adc left 20h:7 (loopback) ac link 1 0 adc right 20h:7 (loopback) 6db -> -15db 0db / 20db 0 1 micbias pin 28 lineinl pin 23 pcbeep pin 19 phone pin 20 mic1 pin 21 lineinr pin 24 mic2 pin 22 avdd pin 25 vref pin 27 agnd pin 24 cap2 pin 32 (1ah[10:8] = 000) & (ms = 00 or 11) 1ah[10:8] = 011 1ah[10:8] = 100 1ah[10:8] = 101 1ah[10:8] = 110 1ah[10:8] = 111 (1ah[10:8] = 000) & (ms = 10) (1ah[10:8] = 000) & (ms = 01) 1ah[2:0] = 011 1ah[2:0] = 100 1ah[2:0] = 111 (1ah[2:0] = 000) & (ms = 00) (1ah[2:0] = 000) & (ms = 10 or 11) (1ah[2:0] = 000) & (ms = 01) 1ah[2:0] = 101 1ah[2:0] = 110 ms = 01 ms = 10 or 11 note: ms bits also affect adc input path from mics note: ms bits also affect sidetone path note: ms bits also affect sidetone path figure 1 audio paths overview
production data WM9715L w pd rev 4.0 december 2007 15 audio inputs the following sections give an overview of the analogue audio input pins and their function. for more information on recommended external components, please refer to the ?applications information? section. line input the lineinl and lineinr inputs are designed to record line level signals, and/or to mix into one of the analogue outputs. both pins are directly connected to the record selector. the record pga adjusts the recording volume, controlled by register 1ch or by the alc function. for analogue mixing, the line input signals pass through a separate pga, controlled by register 10h. the signals can be routed into all three output mixers (headphone, speaker and phone). each linein-to-mixer path has an independent mute bit. when the line inputs are not used, the line-in pga can be switched off to save power (see ?power management? section). lineinl and lineinr are biased internally to the reference voltage vref. whenever the inputs are muted or the device placed into standby mode, the inputs remain biased to vref using special anti- thump circuitry to suppress any audible cli cks w hen changing inputs. register address bit label default description 12:8 lineinl vol 01000 (0db) lineinl input gain 00000: +12db ? (1.5db steps) 11111: -34.5db 4:0 lineinr vol 01000 (0db) lineinr input gain similar to lineinlvol 15 l2h 1 mute linein path to headphone mixer 1: mute, 0: no mute (on) 14 l2s 1 mute linein path to speaker mixer 1: mute, 0: no mute (on) 10h 13 l2p 1 mute linein path to phone mixer 1: mute, 0: no mute (on) table 2 line input control microphone input the mic1 and mic2 inputs are designed for direct connection to single-ended mono, stereo or differential mono microphone. if the microphone is mono, the same signal appears on both left and right channels. in stereo mode, mic1 is routed to the left and mic2 to the right channel. for voice recording, the microphone signal is directly connected to the record selector. the record pga adjusts the recording volume, controlled by register 1ch or by the alc function. for analogue mixing, the signal passes through a separate pga, controlled by register 0eh. the microphone signal can be routed into the phone mixer (for normal phone call operation) and/or the headphone mixer (using register 14h, see ?audio mixers / sidetone control? section), but not into the speaker mixer (to prevent acoustic feedback from the speaker into the microphone). when the microphone inputs are not used, the microphone pga can be switched off to save power (see ?power management? section). mic1 and mic2 are biased internally to the reference voltage vref. whenever the inputs are muted or the device placed into standby mode, the inputs remain biased to vref using special anti-thump circuitry to suppress any audible clicks when changing inputs.
WM9715L production data w pd rev 4.0 december 2007 16 it is also possible to use the lineinl and lineinr pins as a second differential microphone input. this is achieved by setting the ds bit (register 5ch, bit 11) to ?1?. this disables the line-in audio paths and routes the signal from lineinl and lineinr through the differential mic path, as if it came from the mic1 and mic2 pins. only one differential microphone be used at a time. the ds bit only has an effect when ms = 01 (differential mode). register address bit label default description 14 m12p 1 mute mic1 path to phone mixer 1: mute, 0: no mute (on) 13 m22p 1 mute mic2 path to phone mixer 1: mute, 0: no mute (on) 12:8 lmicvol 01000 (0db) left microphone volume only used when ms = 11 similar to micvol 7 20db 0 microphone gain boost (note 1) 1: 20db boost on 0: no boost (0db gain) microphone mode select 00 single-ended mono (left) left = right = mic1 (pin 21) volume controlled by micvol 01 differential mono mode left = right = mic1 ? mic2 volume controlled by micvol 10 single-ended mono (right) left = right = mic2 (pin 22) volume controlled by micvol 6:5 ms 00 11 stereo mode mic1 = left, mic2 = right left volume controlled by lmicvol right volume controlled by micvol 0eh mic volume 4:0 micvol 01000 (0db) microphone volume to mixers 00000: +12db ? (1.5db steps) 11111: -34.5db 5ch additional analogue functions 8 ds 0 differential microphone select 0 : use mic1 and mic2 1: use linel and liner (note 2) table 3 microphone input control note: 1. the 20db gain boost acts on the input to the phone mixer only. a separate microphone boost for recording can be enabled using the boost bit in register 1ah. 2. when the linel and liner are selected for differential microphone select then the mic1 and mic2 input pins become disabled, these signals can therefore not be routed internally to the device. microphone bias the micbias output (pin 28) provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. the internal micbias circuitry is shown below. note that the maximum source current capability for micbias is 3ma. the external biasing resistors and microphone cartridge therefore must limit the micbias current to 3ma.
production data WM9715L w pd rev 4.0 december 2007 17 figure 2 microphone bias schematic phone input pin 20 (phone) is a mono, line level input designed to connect to the receive path of a telephony device. the pin connects directly to the record selector for phone call recording (note: to record both sides of a phone call, one adc channel should record the phone signal while the other channel records the mic signal). the recvol pga adjusts the recording volume, controlled by register 1ch or by the alc function. to listen to the phone signal, the signal passes through a separate pga, controlled by register 0ch. the signal can be routed into the headphone mixer (for normal phone call operation) and/or the speaker mixer (for speakerphone operation), but not into the phone mixer (to prevent forming a feedback loop). when the phone input is not used, the phone-in pga can be switched off to save power (see ?power management? section). phone is biased internally to the reference voltage vref. whenever the input is muted or the device placed into standby mode, the input remains biased to vref using special anti-thump circuitry to suppress any audible clicks when changing inputs. register address bit label default description 15 p2h 1 mute phone path to headphone mixer 1: mute, 0: no mute (on) 14 p2s 1 mute phone path to speaker mixer 1: mute, 0: no mute (on) 0ch phone input 4:0 phone vol 01000 (0db) phone input gain 00000: +12db ? (1.5db steps) 11111: -34.5db table 4 phone input control
WM9715L production data w pd rev 4.0 december 2007 18 pcbeep input pin 19 (pcbeep) is a mono, line level input intended for externally generated signal or warning tones. it is routed directly to the record selector and all three output mixers, without an input amplifier. the signal gain into each mixer can be independently controlled, with a separate mute bit for each signal path. register address bit label default description 15 b2h 1 mute pcbeep path to headphone mixer 1: mute, 0: no mute (on) 14:12 b2hvol 010 (0db) pcbeep to headphone mixer gain 000: +6db ? (3db steps) 111: -15db 11 b2s 1 mute pcbeep path to s peaker mixer 1: mute, 0: no mute (on) 10:8 b2svol 010 (0db) pcbeep to speaker mixer gain 000: +6db ? (3db steps) 111: -15db 7 b2p 1 mute pcbeep path to phone mixer 1: mute, 0: no mute (on) 0ah pcbeep i nput 6:4 b2pvol 010 (0db) pcbeep to phone mixer gain 000: +6db ? (3db steps) 111: -15db table 5 pcbeep control
production data WM9715L w pd rev 4.0 december 2007 19 audio adc the WM9715L has a stereo sigma-delta adc to digitize audio signals. the adc achieves high quality audio recording at low power consumption. the adc sample rate can be controlled by writing to a control register (see ?variable rate audio?). it is independent of the dac sample rate. to save power, the left and right adcs can be separately switched off using the pd11 and pd12 bits, whereas pr0 disables both adcs (see ?power management? section). if only one adc is running, the same adc data appears on both the left and right ac-link slots. high pass filter the WM9715L audio adc incorporates a digital high-pass filter that eliminates any dc bias from the adc output data. the filter is enabled by default. for dc measurements, it can be disabled by writing a ?1? to the hpf bit (register 5ch, bit 3). adc slot mapping by default, the output of the left audio adc appears on slot 3 of the sdatain signal (pin 8), and the right adc data appears on slot 4. however, the adc output data can also be sent to other slots, by setting the ass (adc slot select) control bits as shown below. register address bit label default description 1:0 ass 00 adc to slot m apping 00: left = slot 3, right = slot 4 (default) 01: left = slot 7, right = slot 8 10: left = slot 6, right = slot 9 11: left = slot 10, right = slot 11 5ch additional function control 3 hpf 0 high-pass filter disable 0: filter enabled (for audio) 1: filter disabled (for dc measurements) table 6 adc control
WM9715L production data w pd rev 4.0 december 2007 20 record selector the record selector determines which input signals are routed into the audio adc. the left and right channels can be selected independently. this is useful for recording a phone call: one channel can be used for the rx signal and the other for the tx signal, so that both sides of the conversation are digitized. register address bit label default description 14 boost 0 20db boost 1: boost adc input signal by 20db 0 :no boost 13:12 r2p 11 record to phone path enable 00: left adc and right adc to phone mixer 01 : left adc to phone mixer 10: right adc to phone imixer 11 : muted 11 r2pboost 0 20db boost for adc to phone signal 1: boost signal by 20db 0 :no boost 10:8 recsl 000 left adc signal source 000: mic* (pre-pga) 001-010: reserved (do not use this setting) 011: speaker mix 100: lineinl (pre-pga) 101: headphone mix (left) 110: phone mix 111: phone (pre-pga) 1ah record select 2:0 recsr 000 right adc signal source 000: mic* (pre-pga) 001-010: reserved (do not use this setting) 011: speaker mix 100: lineinr (pre-pga) 101: headphone mix (right) 110: phone mix 111: phone (pre-pga) table 7 audio record selector note: *in stereo mic mode, mic1 is routed to the left adc and mic2 to the right adc. in all mono mic modes, the same signal (mic1, mic2 or mic1-mic2) is routed to both the left and right adcs. see ?microphone input? section for details.
production data WM9715L w pd rev 4.0 december 2007 21 record gain the amplitude of the signal that enters the audio adc is controlled by the record pga (programmable gain amplifier). the pga gain can be programmed either by writing to the record gain register, or by the automatic level control (alc) circuit (see next section). when the alc is enabled, any writes to the record gain register have no effect. two different gain ranges can be implemented: the standard gain range defined in the ac?97 standard, or an extended gain range with smaller gain steps. the alc circuit always uses the extended gain range, as this has been found to result in better sound quality. the output of the record pga can also be mixed into the phone and/or headphone outputs (see ?audio mixers?). this makes it possible to use the alc function for the microphone signal in a smartphone application. register address bit label default description 15 rmu 1 mute audio adc (both channels) 1: mute (off) 0: no mute (on) 14 grl 0 gain range select (left) 0: standard (0 to 22.5db, 1.5db step size) 1: extended (-17.25 to +30db, 0.75db steps) record volume (left) standard (grl=0) extended (grl=1) 13:8 recvoll 000000 xx0000: 0db xx0001: +1.5db ? (1.5db steps) xx1111: +22.5db 000000: -17.25db 000001: -16.5db ? (0.75db steps) 111111: +30db 7 zc 0 zero cross enable 0: record gain changes immediately 1: record gain changes when signal is zero or after time-out 6 grr 0 gain range select (right) similar to grl 1ch record gain 5:0 recvolr 000000 record volume (right) similar to recvoll table 8 record gain register
WM9715L production data w pd rev 4.0 december 2007 22 automatic level control the WM9715L has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. this is achieved by continuously adjusting the pga gain so that the signal level at the adc input remains constant. a digital peak detector monitors the adc output and changes the pga gain if necessary. hold time decay time attack time input signal signal after alc pga gain alc target level figure 3 alc operation the alc function is enabled using the alcsel control bits. when enabled, the recording volume can be programmed between ?6db and ?28.5db (relative to adc full scale) using the alcl register bits. hld, dcy and atk control the hold, decay and attack times, respectively: hold time is the time delay between the peak level detected being below target and the pga gain beginning to ramp up. it can be programmed in power-of-two (2 n ) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7s. alternatively, the hold time can also be set to zero. the hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. decay (gain ramp-up) time is the time that it takes for the pga gain to ramp up across 90% of its range (e.g. from ?15b up to 27.75db). the time it takes for the recording level to return to its target value therefore depends on both the decay time and on the gain adjustment required. if the gain adjustment is small, it will be shorter than the decay time. the decay time can be programmed in power-of-two (2 n ) steps, from 24ms, 48ms, 96ms, etc. to 24.58s. attack (gain ramp-down) time is the time that it takes for the pga gain to ramp down across 90% of its range (e.g. from 27.75db down to ?15b gain). the time it takes for the recording level to return to its target value therefore depends on both the attack time and on the gain adjustment required. if the gain adjustment is small, it will be shorter than the attack time. the attack time can be programmed in power-of-two (2 n ) steps, from 6ms, 12ms, 24ms, etc. to 6.14s. when operating in stereo, the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right pgas, so that the stereo image is preserved. however, the alc function can also be enabled on one channel only. in this case, only one pga is controlled by the alc mechanism, while the other channel runs independently with its pga gain set through the control register.
production data WM9715L w pd rev 4.0 december 2007 23 register address bit label default description 15:14 alcsel 00 (off) alc function select 00 = alc off (pga gain set by register) 01 = right channel only 10 = left channel only 11 = stereo (pga registers unused) note: ensure that recvoll and recvolr settings (reg. 1ch) are the same before entering this mode 13:11 maxgain 111 (+30db) pga gain limit for alc 111 = +30db 110 = +24db ?.(6db steps) 001 = -6db 000 = -12db 8 alczc 0 alc zero cross enable (overrides zc bit in register 1ch) 0: pga gain changes immediately 1: pga gain changes when signal is zero or after time-out 62h alc / noise gate control 9:10 zc timeout 11 programmable zero cross timeout 11 2 17 x mclk period 10 2 16 x mclk period 01 2 15 x mclk period 00 2 14 x mclk period 15:12 alcl 1011 (-12db) alc target ? sets signal level at adc input 0000 = -28.5db fs 0001 = -27.0db fs ? (1.5db steps) 1110 = -7.5db fs 1111 = -6db fs 11:8 hld 0000 (0ms) alc hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ? (time doubles with every step) 1111 = 43.691s 7:4 dcy 0011 (192ms) alc decay (gain ramp-up) time 0000 = 24ms 0001 = 48ms 0010 = 96ms ? (time doubles with every step) 1010 or higher = 24.58s 60h alc control 3:0 atk 0010 (24ms) alc attack (gain ramp-down) time 0000 = 6ms 0001 = 12ms 0010 = 24ms ? (time doubles with every step) 1010 or higher = 6.14s table 9 alc control
WM9715L production data w pd rev 4.0 december 2007 24 maximum gain the maxgain register sets the maximum gain value that the pga can be set to whilst under the control of the alc. this has no effect on the pga when alc is not enabled. peak limiter to prevent clipping when a large signal occurs just after a period of quiet, the alc circuit includes a limiter function. if the adc input signal exceeds 87.5% of full scale (?1.16db), the pga gain is ramped down at the maximum attack rate (as when atk = 0000), until the signal level falls below 87.5% of full scale. this function is automatically enabled whenever the alc is enabled. (note: if atk = 0000, then the limiter makes no difference to the operation of the alc. it is designed to prevent clipping when long attack times are used). noise gate when the signal is very quiet and consists mainly of noise, the alc function may cause ?noise pumping?, i.e. loud hissing noise during silence periods. the WM9715L has a noise gate function that prevents noise pumping by comparing the signal level at the input pins (i.e. before the record pga) against a noise gate threshold, ngth. provided that the noise gate function is enabled (ngat = 1), the noise gate cuts in when: ? signal level at adc [db] < ngth [db] + pga gain [db] + mic boost gain [db] this is equivalent to: ? signal level at input pin [db] < ngth [db] the pga gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). if the ngg bit is set, the adc output is also muted when the noise gate cuts in. the table below summarises the noise gate control register. the ngth control bits set the noise gate threshold with respect to the adc full-scale range. the threshold is adjusted in 1.5db steps. levels at the extremes of the range may cause inappropriate operation, so care should be taken with set?up of the function. note that the noise gate only works in conjunction with the alc function, and always operates on the same channel(s) as the alc (left, right, both, or none). register address bit label default description 7 ngat 0 noise gate function enable 1 = enable 0 = disable 5 ngg 0 noise gate type 0 = pga gain held constant 1 = mute adc output 62h alc / noise gate control 4:0 ngth(4:0) 00000 noise gate threshold 00000: -76.5dbfs 00001: -75dbfs ? 1.5 db steps 11110: -31.5dbfs 11111: -30dbfs table 10 noise gate control
production data WM9715L w pd rev 4.0 december 2007 25 audio dacs stereo dac the WM9715L has a stereo sigma-delta dac that achieves high quality audio playback at low power consumption. digital tone control, adaptive bass boost and 3-d enhancement functions operate on the digital audio data before it is passed to the stereo dac. (contrary to the ac?97 specification, they have no effect on analogue input signals or signals played through the auxiliary dac. nevertheless, the id2 and id5 bits in the reset register, 00h, are set to ?1? to indicate that the WM9715L supports tone control and bass boost.) the dac output has a pga for volume control. the dac sample rate can be controlled by writing to a control register (see ?variable rate audio?). it is independent of the adc sample rate. the left and right dacs can be separately powered down using the pd13 and pd14 control bits, whereas the pr1 bit disables both dacs (see ?power management? section). stereo dac volume the volume of the dac output signal is controlled by a pga (programmable gain amplifier). it can be mixed into the headphone, speaker and phone output paths (see ?audio mixers?). register address bit label default description 15 d2h 1 mute dac path to headphone mixer 1: mute, 0: no mute (on) 14 d2s 1 mute dac path to speaker mixer 1: mute, 0: no mute (on) 13 d2p 1 mute dac path to phone mixer 1: mute, 0: no mute (on) 12:8 dacl vol 01000 (0db) left dac volume 00000: +12db ? (1.5db steps) 11111: -34.5db 18h dac volume 4:0 dacr vol 01000 (0db) right dac volume similar to daclvol 15 amute 0 read-only bit to indicate auto-muting 1: dac auto-muted 0: dac not muted 5ch additional functions (1) 7 amen 0 dac auto-mute enable 1: automatically mutes analogue output of stereo dac if digital input is zero 0: auto-mute off table 11 stereo dac volume control
WM9715L production data w pd rev 4.0 december 2007 26 tone control / bass boost the WM9715L provides separate controls for bass and treble with programmable gains and filter characteristics. this function operates on digital audio data before it is passed to the audio dacs. bass control can take two different forms: ? linear bass control: bass signals are amplified or attenuated by a user programmable gain. this is independent of signal volume, and very high bass gains on loud signals may lead to signal clipping. ? adaptive bass boost: the bass volume is amplified by a variable gain. when the bass volume is low, it is boosted more than when the bass volume is high. this method is recommended because it prevents clipping, and usually sounds more pleasant to the human ear. treble control applies a user programmable gain, without any adaptive boost function. treble, linear bass and 3d enhancement can all produce signals that exceed full-scale. in order to avoid limiting under these conditions, it is recommended to set the dat bit to attenuate the digital input signal by 6db. the gain at the outputs should be increased by 6db to compensate for the attenuation. cut-only tone adjustment and adaptive bass boost cannot produce signals above full- scale and therefore do not require the dat bit to be set. register address bit label default description 15 bb 0 bass mode 0 = linear bass control 1 = adaptive bass boost 12 bc 0 bass cut-off frequency 0 = low (130hz at 48khz sampling) 1 = high (200hz at 48khz sampling) bass intensity code bb=0 bb=1 0000 +9db 15 (max) 0001 +9db 14 0010 +7.5db 13 ? (1.5db steps) ? 0111 0db 8 ? (1.5db steps) ? 1011-1101 -6db 4-2 1110 -6db 1 (min) 11:8 bass 1111 (off) 1111 bypass (off) 6 dat 0 -6db attenuation 0 = off 1 = on 4 tc 0 treble cut-off frequency 0 = high (8khz at 48khz sampling) 1 = low (4khz at 48khz sampling) 08h dac tone control 3:0 trbl 1111 (disabled) treble intensity 0000 or 0001 = +9db 0010 = +7.5db ? (1.5db steps) 1011 to 1110 = -6db 1111 = treble control disabled table 12 dac tone control note: 1. all cut-off frequencies change proportionally with the dac sample rate.
production data WM9715L w pd rev 4.0 december 2007 27 3d stereo enhancement the 3d stereo enhancement function artificially increases the separation between the left and right channels by amplifying the (l-r) difference signal in the frequency range where the human ear is sensitive to directionality. the programmable 3d depth setting controls the degree of stereo expansion introduced by the function. additionally, the upper and lower limits of the frequency range used for 3d enhancement can be selected using the 3dfilt control bits. register address bit label default description 20h general purpose 13 3de 0 (disabled) 3d enhancement enable 5 3dlc 0 lower cut-off frequency 0 = low (200hz at 48khz sampling) 1 = high (500hz at 48khz sampling) 4 3duc 0 upper cut-off frequency 0 = high (2.2khz at 48khz sampling) 1 = low (1.5khz at 48khz sampling) 22h dac 3d control 3:0 3ddepth 0000 3d depth 0000: 0% (minimum 3d effect) 0001: 6.67% ? 1110: 93.3% 1111: 100% (maximum) table 13 stereo enhancement control note: 1. all cut-off frequencies change proportionally with the dac sample rate.
WM9715L production data w pd rev 4.0 december 2007 28 auxiliary dac auxdac is a simple 12-bit mono dac. it can be used to generate dc signals (with the numeric input written into a control register), or ac signals such as telephone-quality ring tones or system beeps (with the input signal supplied through an ac-link slot). in ac mode (xsle = 1), the input data is binary offset coded; in dc mode (xsle = 0), there is no offset. the analogue output of auxdac is routed directly into the output mixers. the signal gain into each mixer can be adjusted at the mixer inputs using control register 12h. in slot mode (xsle = 1), the auxdac also supports variable sample rates (see ?variable rate audio? section). when the auxiliary dac is not used, it can be powered down by setting axe = 0. this is also the default setting. register address bit label default description 15 xsle 0 auxdac input selection 0: from auxdacval (for dc signals) 1: from ac-link slot selected by auxdacslt (for ac signals) 14:12 auxdac slt 000 auxdac input selection 000 ? slot 5, bits 8-19 (with xsle=1) 001 ? slot 6, bits 8-19 (with xsle=1) 010 ? slot 7, bits 8-19 (with xsle=1) 011 ? slot 8, bits 8-19 (with xsle=1) 100 ? slot 9, bits 8-19 (with xsle=1) 101 ? slot 10, bits 8-19 (with xsle=1) 110 ? slot 11, bits 8-19 (with xsle=1) 111 ? reserved (do not use) 64h audac input control 11:0 auxdac val 000h auxdac digital input (with xsle=0) 000h: minimum fffh: full-scale 15 a2h 1 mute auxdac path to headphone mixer 1: mute, 0: no mute (on) 14:12 a2hvol 010 (0db) auxdac to headphone mixer gain 000: +6db ? (3db steps) 111: -15db 11 a2s 1 mute auxdac path to speaker mixer 1: mute, 0: no mute (on) 10:8 a2svol 010 (0db) auxdac to speaker mixer gain 000: +6db ? (3db steps) 111: -15db 7 a2p 1 mute auxdac path to phone mixer 1: mute, 0: no mute (on) 6:4 a2pvol 010 (0db) auxdac to phone mixer gain 000: +6db ? (3db steps) 111: -15db 12h auxdac output control 0 axe 0 0: auxdac off 1: auxdac enabled table 14 auxdac control
production data WM9715L w pd rev 4.0 december 2007 29 note that at low dcvdd voltages, the output range of the auxdac becomes limited, so that its maximum rms output voltage is the lesser of: (dcvdd-0.7) / 2 vrms or avdd / 3.3 vrms under these circumstances, the auxdac cannot convert high digital input values to the correct analogue equivalent; its digital input range must therefore be limited accordingly. if necessary, this limitation can be circumvented by setting gains for the auxdac signal in register 12h, or by using a higher dcvdd voltage.
WM9715L production data w pd rev 4.0 december 2007 30 analogue audio outputs the following sections give an overview of the analogue audio output pins. for more information on recommended external components, please refer to the ?applications information? section. headphone outputs ? hpoutl and hpoutr the hpoutl and hpoutr (pins 39 and 41) are designed to drive a 16 ? or 32 ? headphone or a line output. they can also be used as line-out pins. the output signal is produced by the headphone mixer. the signal volume on hpoutl and hpoutr can be independently adjusted under software control by writing to register 04h. when hpoutl and hpoutr are not used, the output drivers can be disabled to save power (see ?power management? section). both pins remain at the same dc level (the reference voltage vref) when they are disabled, so that no click noise is produced. register address bit label default description 15 mute 1 mute hpoutl and hpoutr 1: mute (off) 0: no mute (on) 13:8 hpoutlvol 000000 (0db) hpoutl volume 000000: 0db (maximum) 000001: -1.5db ? (1.5db steps) 011111: -46.5db 1xxxxx: -46.5db 7 zc 0 zero cross enable 0: change gain immediately 1: change gain only on zero crossings, or after time-out 04h hpoutl / hpoutr volume 5:0 hpoutrvol 00000 (0db) hpoutr volume similar to hpoutlvol table 15 hpoutl / hpoutr control
production data WM9715L w pd rev 4.0 december 2007 31 ear speaker output ? out3 pin 37 (out3) has a buffer that can drive load impedances down to 16 ? . it can be used to: ? drive an ear speaker (phone receiver). the speaker can be connected differentially between out3 and hpoutl, or in single-ended configuration (out3 to hpgnd). the ear speaker output is produced by the headphone mixer. the right signal must be inverted (out3inv = 1), so that the left and right channel are mixed to mono in the speaker [l?(-r) = l+r]. ? eliminate the dc blocking capacitors on hpoutl and hpoutr. in this configuration, out3 produces a buffered midrail voltage (avdd/2) and is connected to the headphone socket?s ground pin (see ?applications information?) ? produce the inverse of the monoout signal, for a differential mono output. note: out3 can only handle one of the above functions at any given time. register address bit label default description 15 mute 1 mute out3 1: mute (buffer off) 0: no mute (buffer on) source of out3 signal 00 inverse of hpoutr (for btl ear speaker) 01 vref (for capless headphone drive) 10 mono mix of both headphone channels (for single-ended ear speaker) 10:9 out3 src 00 11 inverse of monoout (for differential mono output) 7 zc 0 zero cross enable 0: change gain immediately 1: change gain only on zero crossings, or after time-out 16h out3 control 5:0 out3 vol 000000 (0db) out3 volume 000000: 0db (maximum) 000001: -1.5db ? (1.5db steps) 011111: -46.5db 1xxxxx: -46.5db table 16 out3 control
WM9715L production data w pd rev 4.0 december 2007 32 loudspeaker outputs ? lout2 and rout2 the lout2 and rout2 outputs are designed to differentially drive an 8 ? mono speaker. they can also be used as a stereo line-out or headphone output. for speaker drive, the lout2 signal must be inverted (inv = 1), so that the left and right channel are added up in the speaker [r?(-l) = r+l]. register address bit label default description 15 mute 1 mute lout2 and rout2 1: mute (off) 0: no mute (on) 13:8 lout2vol 00000 (0db) lout2 volume 000000: 0db (maximum) 000001: -1.5db ? (1.5db steps) 011111: -46.5db 1xxxxx: -46.5db 7 zc 0 zero cross enable 0: change gain immediately 1: change gain only on zero crossings, or after time-out 6 inv 0 lout2 invert 0 = no inversion (0 phase shift) 1 = signal inverted (180 phase shift) 02h lout2/rout2 volume 5:0 rout2vol 00000 (0db) rout2 volume similar to lout2vol 16h 8 src 0 source of lout2/rout2 signals 0: speaker mixer (for btl speaker) 1: headphone mixer (for stereo output) table 17 lout2 / rout2 control note: 1. for btl speaker drive, it is recommended that lout2vol = rout2vol.
production data WM9715L w pd rev 4.0 december 2007 33 phone output (monoout) the monoout output (pin 33) is intended for connection to the tx side of a wireless chipset. the signal is generated in a dedicated mono mixer; it is not necessarily a mono mix of the stereo outputs hpoutl/r or lout2/rout2 (see ?audio mixers? section). the monoout volume can be controlled by writing to register 06h. when monoout is not used, the output buffer can be disabled to save power (see ?power management? section). the monoout pin remains at the same dc level (the reference voltage on the vref pin), so that no click noise is produced when muting or un-muting. register address bit label default description 15 mute 1 mute monoout 1: mute 0: no mute 7 zc 0 zero cross enable 0: change gain immediately 1: change gain only on zero crossings, or after time-out 06h monoout volume 4:0 monoout vol 00000 (0db) monoout volume 00000: 0db (maximum) 00001: -1.5db ? (1.5db steps) 11111: -46.5db table 18 monoout control thermal sensor the speaker and headphone outputs can drive very large currents. to protect the WM9715L from becoming too hot, a thermal sensor has been built in. if the chip temperature reaches approximately 150 c, and the ent bit is set, the WM9715L de-asserts bit 11 in register 54h, which can be set up to generate an interrupt to the cpu (see ?interrupt control? section). register address bit label default description 5ch 2 ent 0 enable thermal sensor 0: disabled 1: enabled 54h 11 ti 1 thermal sensor (interrupt bit) 1: temperature below 150 c 0: temperature above 150 c see also ?interrupt control? section. table 19 thermal cutout control
WM9715L production data w pd rev 4.0 december 2007 34 digital audio (spdif) output the WM9715L supports the spdif standard using the spdif_out pin as its output. register 3ah is a read/write register that controls spdif functionality and manages bit fields propagated as channel status (or sub-frame in the v case). with the exception of v, this register should only be written to when the spdif transmitter is disabled (spdif bit in register 2ah is ?0?). once the desired values have been written to this register, the contents should be read back to ensure that the sample rate in particular is supported, then spdif validity bit spcv in register 2ah should be read to ensure the desired configuration is valid. only then should the spdif enable bit in register 2ah be set. this ensures that control and status information start up correctly at the beginning of spdif transmission. register address bit label default description 10 spcv 0 spdif validity bit (read-only) 5:4 spsa 01 spdif slot assignment (adco = 0) 00: slots 3, 4 01: slots 6, 9 10: slots 7, 8 11: slots 10, 11 2ah extended audio 2 sen 0 spdif output enable 1 = enabled, 0 = disabled note: bit 5 of register 4ch and bit 5 of register 56h must be ?0? before the spdif output can be enabled. 15 v 0 validity bit; ?0? indicates frame valid, ?1? indicates frame not valid 14 drs 0 indicates that the WM9715L does not support double rate spdif output (read-only) 13:12 spsr 10 indicates that the wm 9715l only supports 48khz sampling on the spdif output (read- only) 11 l 0 generation level; programmed as required by user 10:4 cc 0000000 category code; programmed as required by user 3 pre 0 pre-emphasis; ?0? indicates no pre-emphasis, ?1? indicates 50/15us pre-emphasis 2 copy 0 copyright; ?0? indicates copyright is not asserted, ?1? indicates copyright 1 audib 0 non-audio; ?0? indicates data is pcm, ?1? indicates non-pcm format (e.g. dd or dts) 3ah spdif control register 0 pro 0 professional; ?0? indicates consumer, ?1? indicates professional 5ch additional function control 4 adco 0 source of spdif data 0: spdif data comes from sdataout (pin 5), slot selected by spsa 1: spdif data comes from audio adc table 20 spdif output control
production data WM9715L w pd rev 4.0 december 2007 35 audio mixers mixer overview the WM9715L has three separate low-power audio mixers to cover all audio functions required by smartphones, pdas and handheld computers. the diagram below shows the routing of the analogue audio signals into the mixers. the numbers at the mixer inputs refer to the control register bits that control the volume and muting for that particular signal. phone_in pcbeep line_in stereo headphone / headset hpoutl hpoutr hpvol (reg 04h) monoout (phone tx) out3vol (reg 16h) lout2 rout2 out2vol (reg 02h) loud speaker out3 ear speaker 0ch [4:0] 10h [12:8,4:0] 18h [12:8,4:0] record select 0eh [12:8,4:0] micr micl diff / stereo/ mono (reg 20h) stereo dac aux dac (12-bit) 1ch / alc 0/20 db 0eh [7] m u x monoout vref 18h [15] 10h [15] 14h [15:12] 14h [11:7] 0ch [15] 12h [15:12] 18h [13] 10h [13] 0eh [14,13] 1ah [13:11] 0ah [15:12] head phone/ ear speaker mix phone mix 12h [7:4] 0ah [7:4] -1 m u x 12h [11:8] 18h [14] 10h [14] 0ah [11:8] 0ch [14] back speaker mix src (reg 16h) out3src (reg 16h) stereo adc m u x phone mix headphone mix back spkr mix inv (reg 02h) 1ah [14] 0/20 db figure 4 audio mixer overview headphone mixer the headphone mixer drives the hpoutl and hpoutr outputs. it also drives out3, if this pin is connected to an ear speaker (phone receiver). the following signals can be mixed into the headphone path: ? phone (controlled by register 0ch, see ?audio inputs?) ? line_in (controlled by register 10h, see ?audio inputs?) ? the output of the record pga (see ?audio adc?, ?record gain?) ? the stereo dac signal (controlled by register 18h, see ?audio dacs?) ? the mic signal (controlled by register 0eh, see ?audio inputs?) ? pc_beep (controlled by register 0ah, see ?audio inputs?) ? the auxdac signal (controlled by register 12h, see ?auxiliary dac?) in a typical smartphone application, the headphone signal is a mix of phone and sidetone (for phone calls) and the stereo dac signal (for music playback).
WM9715L production data w pd rev 4.0 december 2007 36 speaker mixer the speaker mixer drives the lout2 and rout2 output. the following signals can be mixed into the speaker path: ? phone (controlled by register 0ch, see ?audio inputs?) ? line_in (controlled by register 10h, see ?audio inputs?) ? the stereo dac signal (controlled by register 18h, see ?audio dacs?) ? pc_beep (controlled by register 0ah, see ?audio inputs?) ? the auxdac signal (controlled by register 12h, see ?auxiliary dac?) in a typical smartphone application, the speaker signal is a mix of auxdac (for system alerts or ring tone playback), phone (for speakerphone function), and pc_beep (for externally generated ring tones). mono mixer the mono mixer drives the monoout pin. the following signals can be mixed into monoout: ? line_in (controlled by register 10h, see ?audio inputs?) ? the output of the record pga (see ?audio adc?, ?record gain?) ? the stereo dac signal (controlled by register 18h, see ?audio dacs?) ? the mic signal (controlled by register 10h, see ?audio inputs?) ? pc_beep (controlled by register 0ah, see ?audio inputs?) ? the auxdac signal (controlled by register 12h, see ?auxiliary dac?) in a typical smartphone application, the monoout signal is a mix of the amplified microphone signal (possibly with automatic gain control) and (if enabled) an audio playback signal from the stereo dac or the auxiliary dac. side tone control the side tone path is into the headphone mixer and is either from the mic or alc path (with no 20db boost) register address bit label default description 15 stm 1 mic side tone select 0: selected 1 : not selected (path muted) 14:12 stvol 010 (0db) mic sidetone volume 000 : +6db (max.) 001: +3db ? (3db steps) 111 : -15db (min.) 11:10 alcm 11 alc side tone select 11: mute 10: mono ? left 01: mono ? right 00: stereo 14h sidetone control 9:7 alcvol 010 (0db) alc sidetone volume similar to stvol table 21 side tone control
production data WM9715L w pd rev 4.0 december 2007 37 variable rate audio / sample rate conversion by using an ac?97 rev2.2 compliant audio interface, the WM9715L can record and playback at all commonly used audio sample rates, and offer full split-rate support (i.e. the dac, adc and auxdac sample rates are completely independent of each other ? any combination is possible). the default sample rate is 48khz. if the vra bit in register 2ah is set and the appropriate block is enabled, then other sample rates can be selected by writing to registers 2ch, 32h and 2eh. the ac- link continues to run at 48k frames per second irrespective of the sample rate selected. however, if the sample rate is less than 48khz, then some frames do not carry an audio sample. register address bit label default description 2ah extended audio stat/ctrl 0 vra 0 (off) variable rate audio 0: off (dac and adc run at 48khz) 1: on (sample rates determined by registers 2ch, 2eh and 32h) 2ch audio dac sample rate 15:0 dacsr bb80h (48khz) audio dac sample rate 1f40h: 8khz 2b11h: 11.025khz 2ee0h: 12khz 3e80h: 16khz 5622h: 22.05khz 5dc0h: 24khz 7d00h: 32khz ac44h: 44.1khz bb80h: 48khz any other value defaults to the nearest supported sample rate 32h audio adc sample rate 15:0 adcsr bb80h (48khz) audio adc sample rate similar to dacsr note writing to these bits has no effect when adc is disabled 2eh auxdac sample rate 15:0 auxdac sr bb80h (48khz) auxdac sample rate similar to dacsr table 22 audio sample rate control when the audio adc is disabled, its sample rate cannot be changed (i.e. writing to the adcsr bits has no effect). the following sequence of register writes is therefore recommended for changing the adc sample rate: 1. set pd11 and/or pd12 = 0 in register 24h as appropriate for left/right/stereo adc operation 2. set pr0 = 0 in register 26h to enable the audio adc(s) 3. set vra = 1 in register 2ah to enable variable rate audio 4. set adcsr in register 32h to the appropriate value for the desired sample rate
WM9715L production data w pd rev 4.0 december 2007 38 touchpanel interface the WM9715L includes a touchpanel driver and digitiser circuit for use with 4-wire or 5-wire resistive touchpanels. the following functions are implemented: ? x co-ordinate measurement ? y co-ordinate measurement ? pen down detection, with programmable sensitivity ? touch pressure measurement (4-wire touchpanel only) ? auxiliary measurement from comp1/aux1 (pin 29), comp2/aux2 (pin 30), bmon/aux3 (pin 31), or wiper/aux4 (pin 12) the touchpanel digitiser uses a very low power, 12-bit successive approximation type adc. the same adc can also be used for battery and auxiliary measurements (see the ?battery alarm and battery measurement? and ?auxiliary adc inputs? sections). an on-chip switch matrix connects each touchpanel terminal to the supply voltage tpvdd, to ground (tpgnd), or to the adc input, as required. sar adc x+/br (14) x-/tl (16) tpgnd y+/tr (15) y-/bl (17) wiper/aux4 (12) aux3/bmon (31) zero power comparator i p tpvdd r pu pen down aux2 (30) aux1 (29) 20k 10k figure 5 touchpanel switch matrix principle of operation - four-wire touchpanel four-wire touchpanels are connected to the WM9715L as follows: ? right side contact = x+ (pin 14) ? left side contact = x- (pin 16) ? top side contact = y+ (pin 15) ? bottom side contact = y- (pin 17)
production data WM9715L w pd rev 4.0 december 2007 39 the principle of operation is illustrated below (note: the illustrations assume that the top plate is used for x and the bottom plate for y measurements, although the reverse is also possible). figure 6 x co-ordinate measurement on 4-wire touchpanel for an x co-ordinate measurement, the x+ pin is internally switched to vdd and x- to gnd. the x plate becomes a potential divider, and the voltage at the point of contact is proportional to its x co- ordinate. this voltage is measured on the y+ and y- pins, which carry no current (hence there is no voltage drop in r y+ or r y- ). due to the ratiometric measurement method, the supply voltage does not affect measurement accuracy. the voltage references vref+ and vref- are taken from after the matrix switches, so that any voltage drop in these switches has no effect on the adc measurement. figure 7 y co-ordinate measurement on 4-wire touchpanel y co-ordinate measurements are similar to x co-ordinate measurements, with the x and y plates interchanged. figure 8 pen down detection on 4-wire touchpanel pen down detection uses a zero power comparator (effectively a cmos logic gate) with an internal, programmable pull-up resistor r pu that controls pen-down sensitivity. increasing r pu makes the touchpanel less sensitive to touch, while lowering r pu makes it more sensitive.
WM9715L production data w pd rev 4.0 december 2007 40 when the touchpanel is not being touched, no current flows in the circuit, and the pendown signal is low. when the panel is touched with a pen or finger, current flows through r pu and the panel, and the comparator output goes high. the pendown signal can be transmitted through the pendown pin (see ?interrupt control? section). additionally, its state is reflected in the pndn bit (register 7ah, bit 15) and the interrupt logic block (register 54h, bit 13), where it can wake the WM9715L from sleep mode (see ?interrupt control? section). figure 9 touch pressure measurement on 4-wire touchpanel touch pressure can be determined indirectly by measuring the contact resistance r c between the top and bottom plates. r c decreases as the touch pressure on the panel increases. the WM9715L measures r c by sending a constant current i p through the touchpanel and measuring the potential on each plate. the two values are subtracted in the digital domain to obtain the potential difference, which is proportional to r c . to suit different types of touchpanels, the magnitude of i p can be set to either 400 a or 200 a using the pil control bit. principle of operation - five-wire touchpanel five-wire touchpanels are connected to the WM9715Las follows: ? top sheet contact = wiper/aux4 (pin 12) ? top left corner of bottom sheet = tl (pin 16) ? top right corner of bottom sheet = tr (pin 15) ? bottom left corner of bottom sheet = bl (pin 17) ? bottom right corner of bottom sheet = br (pin 14) figure 10 x co-ordinate measurement on 5-wire touchpanel
production data WM9715L w pd rev 4.0 december 2007 41 for an x co-ordinate measurement, the top left and bottom left corners of the touchpanel are grounded internally to the wm9715, while the top right and bottom right contacts are connected to tpvdd. the bottom plate becomes a potential divider with a voltage gradient in the x direction. the voltage at the point of contact is proportional to its x co-ordinate. this voltage is measured on the top pin and converted to a digital value by the adc. due to the ratiometric measurement method, the supply voltage does not affect measurement accuracy. the voltage references vref+ and vref- are taken from after the matrix switches, so that any voltage drop in these switches has no effect on the adc measurement. figure 11 y co-ordinate measurement on 5-wire touchpanel y co-ordinate measurements are similar to y co-ordinate measurements. however, the voltage gradient on the bottom plate is in the y direction instead of the x direction. this is achieved by grounding the bottom left and bottom right corners of the touchpanel, and connecting the top left and top right contacts to tpvdd. figure 12 pen down detection on 5-wire touchpanel pen down detection works in a similar fashion for both 4-wire and 5-wire touchpanels (see four-wire touchpanel operation). on a 5-wire touchpanel, all four contacts of the bottom plate are grounded, and the top plate contact is connected to the internal programmable pull-up resistor, r pu .
WM9715L production data w pd rev 4.0 december 2007 42 controlling the touchpanel digitiser all touchpanel functions are accessed and controlled through the ac-link interface. physical characteristics the physical characteristics of the touchpanel interface are controlled through register 78, as shown below. register address bit label default description 12 45w 0 (4-wire) touchpanel type selection 0: 4-wire 1: 5-wire 0:5 rpu 000001 (68k ? ) internal pull-up resistor for pen detection 000000: r eserved (do not use this setting) 000001: r pu /1 = typ 68k ? (most sensitive) 000010: r pu /2 = typ 34k ? ? (pull-up = r pu / binary value of rpu) (refer to page 9 for r pu specification) 78h 8 pil 0 (200 a) current used for pressure measurement 0: i p = 200 a 1: i p = 400 a table 23 touchpanel digitiser control (physical characteristics) power management to save power, the touchpanel digitiser and the pen-down detector can be independently disabled when they are not used. the power consumption of the pen-down detector is normally negligible, except when the pen is down. the state of the digitiser and pen down detector is controlled by the following bits. register address bit label default description 15:14 prp 00 pen adc/aux adc enable 00 ? pen digitiser off, pen detect off, no wake-up on pen down (default) 01 ? pen digitiser powered off, pen detect enabled, touchpanel digitiser wakes up (changes to state 11) on pen-down 10 ? pen digitiser off, pen detect enabled, no wake-up on pen down 11 ? pen digitiser and pen detect enabled 78h 13 rpr 0 wake-up on pen-down mode 0: wake-up the ac-link only (hold sdatain high until controller sends warm reset or cold reset) 1: wake-up the WM9715L without waiting for a reset signal from the controller table 24 touchpanel digitiser control (power management)
production data WM9715L w pd rev 4.0 december 2007 43 initiation of measurements the WM9715L touchpanel interface supports both polling routines and dma (direct memory access) to control the flow of data from the touchpanel adc to the host cpu. in a polling routine, the cpu starts each measurement individually by writing to the poll bit (register 76h, bit 15). this bit automatically resets itself when the measurement is completed. register address bit label default description 10 ctc 0 0: polling mode 1: continuous mode (for dma) 15 poll 0 writing ?1? initiates a measurement 76h 9:8 cr 00 continuous mode rate (del 1111) 00: 93.75 hz (every 512 ac-link frames) 01: 187.5 hz (every 256 ac-link frames) 10: 375hz (every 128 ac-link frames) 11: 750hz (every 64 ac-link frames) continuous mode rate (del = 1111) 00: 8 khz (every six ac-link frames) 01: 12 khz (every four ac-link frames) 10: 24 khz (every other ac-link frame) 11: 48 khz (every ac-link frame) 78h 11 pden 0 0: measure regardless of pen status 1: measure only when pen is down (when ctc=0 and poll=1, measurement is delayed until pen-down; when ctc=1, measurements are stopped on pen-up) table 25 touchpanel digitiser control (initiation of measurements) in continuous mode (ctc = 1), the WM9715L autonomously initiates measurements at the rate set by cr, and supplies the measured data to the cpu on one of the unused ac?97 time slots. dma- enabled cpus can write the data directly into a fifo without any intervention by the cpu core. this reduces cpu loading and speeds up the execution of user programs in handheld systems. note that the measurement frequency in continuous mode is also affected by the del bits (see ?touchpanel settling time?). the faster rates achieved when del = 1111 may be useful when the adc is used for auxiliary measurements. measurement types the adcsel control bits determine which type of measurement is performed (see below). register address bit label default description 14:12 adcsel 000 measurement type (adc input selector) 000: no measurement 001: x co-ordinate measurement 010: y co-ordinate measurement 011: pressure measurement 100: comp1/aux1 measurement (pin 29) 101: comp2/aux2 measurement (pin 30) 110: bmon/aux3 measurement (pin 31) 111: wiper/aux4 measurement (pin 12) 76h 11 coo 0 enable co-ordinate mode 0: single measurement according to adcsel 1: x, then y, then additional measurement indicated by adcsel table 26 touchpanel digitiser control (measurement types)
WM9715L production data w pd rev 4.0 december 2007 44 when coo is ?0?, the WM9715L performs one type of measurement once (in polling mode) or continuously (in continuous mode). the co-ordinate mode (coo = ?1?) makes it easier to obtain co-ordinate pairs rather than single co- ordinates. in polling-coordinate mode (ctc = ?0?, coo = ?1?), the WM9715L performs an x measurement, followed by a y measurement, followed by an additional measurement determined by adcsel, then stops. in continuous-coordinate mode (ctc = ?1?, coo = ?1?), the WM9715L continuously repeats a sequence consisting of an x-co-ordinate measurement, followed by a y co- ordinate measurement, followed by an additional measurement determined by adcsel (if adcsel = 000, the sequence is xyxyxy? only). data readback the output data word of the touchpanel interface consists of three parts: ? pen status (1 bit) ? this is also passed to the interrupt logic block, which can be programmed to generate an interrupt and/or wake up the WM9715L on pen down (see ?interrupt control?). ? output data from the touchpanel adc (12 bits) ? adcsrc: 3 additional bits that indicate the source of the adc data. with coo = ?0?, adcsrc echoes adcsel. however, in co-ordinate mode (coo = ?1?), the WM9715L schedules different types of measurements autonomously and sets the adcsrc bits accordingly (see ?measurement types?). this data is stored in register 7ah, and can be retrieved by reading the register in the usual manner (see ac-link interface section). additionally, the data can also be passed to the controller on one of the ac-link time slots not used for audio functions. to minimize cpu loading, it is recommended to use interrupt-driven methods rather than polling routines for reading touchpanel data. however, where polling routines are used, two methods are available for determining when a measurement has finished: ? reading back the poll bit. if it has been reset to ?0?, then the measurement has finished. ? reading back 7ah until the new data appears register address bit label default description 15 pndn 0 pen status (read-only) 0: pen up 1: pen down 14:12 adcsrc 000 touchpanel adc source 000: no measurement 001: x co-ordinate measurement 010: y co-ordinate measurement 011: pressure measurement (4-wire touchpanels only) 100: comp1/aux1 measurement (pin 29) 101: comp2/aux2 measurement (pin 30) 110: bmon/aux3 measurement (pin 31) 111: wiper/aux4 measurement (pin 12) 7ah or ac-link slot selected by slt 11:0 adcd 000h touchpanel adc data (read-only) bit 11 = msb bit 0 = lsb 78h 9 wait 0 0: no effect (new adc data overwrites unread data in register 7ah) 1: new data is held back, and measurements delayed, until register 7ah is read) table 27 touchpanel digitiser data to avoid losing data that has not yet been read, the WM9715L can delay overwriting register 7ah with new data until the old data has been read. this function is enabled using the wait bit.
production data WM9715L w pd rev 4.0 december 2007 45 if the slen bit is set to ?1?, then the touchpanel data appears on the ac-link slot selected by the slt control bits, as shown below. the slot 0 ?tag? bit corresponding to the selected time slot is asserted whenever there is new data on that slot. register address bit label default description 3 slen 0 slot readback enable 0: disabled (readback through register only) 1: enable (readback slot selected by slt) 76h 2:0 slt 110 ac?97 slot selection for touchpanel data 000: slot 5 001: slot 6 ? 101: slot 10 110: slot 11 111: reserved table 28 returning touchpanel data through an ac-link time slot touchpanel settling time for accurate touchpanel measurements, some settling time may be required between the switch matrix applying a voltage across the touchpanel plate and the adc sampling the signal. this time delay function is built into the WM9715L and can be programmed as shown below. register address bit label default description 76h 7:4 del 0000 (1 frame) touchpanel adc settling time table 29 touchpanel settling time control (1) del delay (ac-link frames) delay (time) 0000 1 20.8 s 0001 2 41.7 s 0010 4 83.3 s 0011 8 167 s 0100 16 333 s 0101 32 667 s 0110 48 1ms 0111 64 1.33ms 1000 96 2ms 1001 128 2.67ms 1010 160 3.33ms 1011 192 4ms 1100 224 4.67ms 1101 256 5.33ms 1110 288 6ms 1111 no delay, switch matrix always on table 30 touchpanel settling time control (2) the total time for co-ordinate or auxiliary measurements to complete is the delay time del, plus one ac-link frame (20.8 s). for a pressure measurement, the time taken is del plus two ac-link frames (41.6 s).
WM9715L production data w pd rev 4.0 december 2007 46 setting del to ?1111? reduces the settling time to zero, i.e. measurements begin immediately. this mode is intended for fast sampling on aux inputs. it is not intended for touchpanel digitisation. there are several side-effects when del is set to ?1111?: ? co-ordinate mode does not work, i.e. the WM9715L behaves as if coo = 0, even if coo = 1 (see ?measurement types?) ? if x / y co-ordinate or touch pressure measurements are selected (adcsel = 001, 010 or 011), then the switch matrix is constantly on, and current constantly flows in the touchpanel. this increases power consumption in the system, and is therefore not recommended for battery powered systems ? in continuous mode (ctc = 1), setting del = 1111 increases the sampling rate of the touchpanel adc (see ?initiation of measurements?)
production data WM9715L w pd rev 4.0 december 2007 47 auxiliary adc inputs the adc used for touchpanel digitisation can also be used for auxiliary measurements, provided that it is enabled (register 78h, prp = 11). the WM9715L has four pins that can be used as auxiliary adc inputs: ? comp1 / aux1 (pin 29) ? comp2 / aux2 (pin 30) ? bmon / aux3 (pin 31) ? wiper / aux4 (pin 12) note that pin 12 connects to the wiper of a 5-wire touchpanel wiper function. auxiliary measurements taken on pin 12 are only meaningful when it is not connected to a touchpanel (i.e. a 4-wire touchpanel, or no touchpanel at all, is used). pins 29 and 30 are also used as comparator inputs (see battery alarm and battery measurement), but auxiliary measurements can still be taken on these pins at any time. for the use of pin 31 see the ?battery alarm and battery measurement? section, note that the measured value from the bmon/aux3 pin will be 1/3 of the actual value due to the potential divider on this pin. the adcsel control bits select between different adc inputs, as shown below. register address bit label default description 76h touchpanel digitiser control 14:12 adcsel 000 touchpanel adc input selector 000: no measurement 001-011: touchpanel measurement (please refer to touchpanel digitiser section) 100: comp1 / aux1 measurement (pin 29) 101: comp2 aux2 measurement (pin 30) 110: bmon / aux3 measurement (pin 31) 111: wiper / aux 4 measurement (pin 12) table 31 auxiliary adc measurements auxiliary adc measurements are initiated in the same way as touchpanel measurements, and the data is returned in the same manner. please refer to the ?controlling the touchpanel interface? section. battery measurement using the bmon/aux3 pin bmon/aux3 (pin 31) has the capability to take inputs up to 5 volts (assuming avdd=3.3v) by dividing down the input signal. the internal potential divider has a total resistance of 30k ? . however, it is only connected to the pin when an aux3 measurement is requested, and remains connected for the duration of one ac-link frame (20.83 s, assuming a 24.576mhz clock crystal is used). the effective input impedance of bmon/aux3 is therefore given by: r bmon = 30k ? 48khz / [bmon sampling rate] for example, if bmon is sampled ten times per second, the effective input resistance is 30k ? 48khz / 10hz = 144m ? .
WM9715L production data w pd rev 4.0 december 2007 48 battery alarm and analogue comparators the battery alarm function differs from battery measurement in that it does not actually measure the battery voltage. battery alarm only indicates ?ok?, ?low? or ?dead?. the advantage of the battery alarm function is that it does not require a clock and can therefore be used in low-power sleep or standby modes. figure 13 battery alarm example schematic the typical schematic for a dual threshold battery alarm is shown above. this alarm has two thresholds, ?dead battery? (comp1) and ?low battery? (comp2). r1, r2 and r3 set the threshold voltages. their values can be up to about 1m ? in order to keep the battery current [i alarm = v batt / (r1+r2+r3)] to a minimum (higher resistor values may affect the accuracy of the system as leakage currents into the input pins become significant). ? dead battery alarm: comp1 triggers when v batt < vref (r1+r2+r3) / (r2+r3) a dead battery alarm is the highest priority of interrupt in the system. it should immediately save all unsaved data and shut down the system. the gp15, gs15 and gw15 bits must be set to generate this interrupt. ? low battery alarm: comp2 triggers when v batt < vref (r1+r2+r3) / r3 a low battery alarm has a lower priority than a dead battery alarm. since the threshold voltage is higher than for a dead battery alarm, there is enough power left in the battery to give the user a warning and/or shut down ?gracefully?. when v batt gets close to the low battery threshold, spurious alarms are filtered out by the comp2 delay function. the purpose of the capacitor c is to remove from the comparator inputs any high frequency noise or glitches that may be present on the battery (for example, noise generated by a charge pump). it forms a low pass filter with r1, r2 and r3. ? low pass cutoff f c [hz] = 1/ (2 c (r1 || (r2+r3))) provided that the cutoff frequency is several orders of magnitude lower than the noise frequency f n , this simple circuit can achieve excellent noise rejection. ? noise rejection [db] = 20 log (f n / f c ) the circuit shown above also allows for measuring the battery voltage v batt . this is achieved simply by setting the touchpanel adc input to be either comp1 (adcsel = 100) or comp2 (adcsel = 101) (see also auxiliary adc inputs).
production data WM9715L w pd rev 4.0 december 2007 49 the WM9715L has two on-chip comparators that can be used to implement a battery alarm function, or other functions such as a window comparator. each comparator has one of its inputs tied to any one of three device pins and the other tied to a voltage reference. the voltage reference can be either internally generated (vref = avdd/2) or externally connected on aux4 (pin 12). the comparator output signals can be used to send an interrupt to the cpu via the genirq pin, and / or to wake up the WM9715L from sleep mode (see ?interrupt control? for details). register address bit label default description 15 cp1 1 comp1 polarity (see also ?interrupt control?) 0: alarm when comp1 voltage is below vref 1: alarm when comp1 voltage is above vref 4eh 14 cp2 1 comp2 polarity (see also ?interrupt control?) 0: alarm when comp2 voltage is below vref 1: alarm when comp2 voltage is above vref 58h 15:13 comp2 del 0 low battery alarm delay 000: no delay 001: 0.17s (2 13 = 8192 ac-link frames) 010: 0.34s (2 14 = 16384 ac-link frames) 011: 0.68s (2 15 = 32768 ac-link frames) 100: 1.4s (2 16 = 65536 ac-link frames) 101: 2.7s (2 17 = 131072 ac-link frames) 110: 5.5s (2 18 = 262144 ac-link frames) 111: 10.9s (2 19 = 524288 ac-link frames) table 32 comparator control register address bit label default description comparator 1 reference voltage 0 vref = avdd/2 14 c1ref 0 1 wiper/aux4 (pin 12) comparator 1 signal source 00 avdd/2 when c1ref=?1?. otherwise comparator 1 is powered down 01 comp1/aux1 (pin 29) 10 comp2/aux2 (pin 30) 13:12 c1src 00 11 bmon/aux3 (pin 31) comparator 2 reference voltage 0 vref = avdd/2 11 c2ref 0 1 wiper/aux4 (pin 12) comparator 2 signal source 00 avdd/2 when c2ref=?1?. otherwise comparator 2 is powered down 01 comp1/aux1 (pin 29) 10 comp2/aux2 (pin 30) 5ch additional analogue functions 10:9 c2src 00 11 bmon/aux3 (pin 31) table 33 comparator reference and source control
WM9715L production data w pd rev 4.0 december 2007 50 comp2 delay function comp2 has an optional delay function for use when the input signal is noisy. when comp2 triggers and the delay is enabled (i.e. comp2del is non-zero), then the c2i bit in register 54h does not change state immediately, and no interrupt is generated. instead, the WM9715L starts a delay timer and checks comp2 again after the delay time has passed. if comp2 is still active, then the interrupt bit is set and an interrupt may be generated (depending on the state of the gw14 bit). if comp2 is no longer active, the interrupt bit is not set, i.e. all register bits are as if comp2 had never triggered. note: if comp2 triggers while the WM9715L is in sleep mode, and the delay is enabled, then the device starts the on-chip crystal oscillator in order to count the time delay. comp2 triggers start timer comp2? wait time=comp2del shut down timer inactive active set gi14 end end [false alarm] comp2 del? non-zero c2w? 0 end 1 000 figure 14 comp2 delay flow chart
production data WM9715L w pd rev 4.0 december 2007 51 interrupt control the WM9715L has three interrupt pins: ? adcirq is a dedicated interrupt pin to indicate that auxadc data is available for reading (see ?touchpanel interface?) ? pendown is a dedicated interrupt pin to indicate that the resistive touchpanel connected to the WM9715L is being touched (see ?touchpanel interface?) ? genirq is a general-purpose interrupt pin, which can indicate a number of different events. the adcirq pin in a typical use case with touchscreen measurements running continuously, ?auxadc data available? is the most frequent type of interrupt event from the WM9715L. in the interest of minimizing software overheads, it is recommended to use the dedicated adcirq pin to transmit this type of interrupt. the adcirq output is enabled using registers 56h and 4ch. register address bit label default description 4ch 4 gc4 1 56h 4 ge4 1 adcirq output enable adcirq is enabled when both gc4 and ge4 are set to ?0?. to disable adcirq, set both bits to ?1?. other combinations (0/1, 1/0) are reserved. table 34 enabling the adcirq pin the pendown pin in a typical use case, pendown is the second most frequent type of interrupt after adcirq. in the interest of minimizing software overheads, it is recommended to use the dedicated pendown pin to transmit this type of interrupt. the pendown output is enabled using registers 56h and 4ch. register address bit label default description 4ch 3 gc3 1 56h 3 ge3 1 pendown output enable pendown is enabled when both gc4 and ge4 are set to ?0?. to disable pendown, set both bits to ?1?. other combinations (0/1, 1/0) are reserved. table 35 enabling the pendown pin the genirq pin the genirq pin transmits a logical or of up to five individual interrupt events: ? over-temperature (see ?thermal sensor?) ? comp1 events, e.g. dead battery alarm (see ?battery alarm and analogue comparators?) ? comp2 events, e.g. low battery alarm (see ?battery alarm and analogue comparators?) ? adcirq ? pendown when the host processor receives an interrupt, it needs to read register 54h in order to determine which event triggered the interrupt. as a result, genirq is best suited for interrupts that occur rarely, and where longer response times can be tolerated. adcirq or pendown interrupts should only be
WM9715L production data w pd rev 4.0 december 2007 52 transmitted through the genirq pin if the dedicated interrupt pins cannot be used (e.g. if there are insufficient pins available on the host processor). the genirq output is enabled using registers 56h and 4ch. its polarity can be controlled using the irqinv bit in register 58h, and interrupt wake-up (i.e. re-activating the ac-link when an interrupt occurs after the WM9715L has been put into sleep mode, see ?power management?) is enabled by the wakeen bit in register 58h. register address bit label default description 4ch 2 gc2 1 56h 2 ge2 1 genirq output enable genirq is enabled when both gc4 and ge4 are set to ?0?. to disable genirq, set both bits to ?1?. other combinations (0/1, 1/0) are reserved. 0 irqinv 0 inverts the genirq signal (pin 45) 0: genirq signal not inverted 1: genirq signal inverted 58h additional functional control 1 wake en 0 enables WM9715L wake-up on interrupt 0: disabled 1: enabled table 36 controlling the genirq pin the global interrupt signal genirq is a logical or of selected internal interrupts, each of which may have its polarity inverted and/or go through a ?sticky? circuit if desired. this is illustrated below. figure 15 interrupt logic equivalent circuit each genirq interrupt source has an associated bit in register 54h for readback. interrupt source reg 54h bit description thermal cutout (t) 11 internal thermal cutout signal, indicates when internal temperature reaches approximately 150 c (see ?thermal sensor?) auxadc data available (a) 12 internal ada (adc data available) signal enabled only when auxiliary adc is active pen-down (p) 13 internal pendown signal enabled only when pen-down detection is active comp2 (c2) 14 internal comp2 output (low battery alarm) enabled only when comp2 is on comp1 (c1) 15 internal comp1 output (dead battery alarm) enabled only when comp1 is on table 37 interrupt sources
production data WM9715L w pd rev 4.0 december 2007 53 the processing of internal interrupt signals is controlled through registers 4eh to 52h, as shown below. register address label default description note: x identifies a particular interrupt (t, a, p, c2 or c1, as per table 37) 4eh x p 1 interrupt polarity 0: active low 1: active high [ x i bit = internal interrupt signal xnor x p] 50h x s 0 interrupt sticky 1: sticky (gi n bit remains set until read, even after internal interrupt signal becomes inactive) 0: not sticky (gi n bit follows internal interrupt signal) 52h x w 0 interrupt enable 1: wake up (generate interrupts from this pin) 0: no wake-up (no interrupts generated) 54h x i n/a interrupt status read: returns status of each interrupt bit write: writing ?0? clears sticky bit table 38 genirq interrupt control the following procedure is recommended for handling genirq interrupts: when the controller receives a genirq interrupt, check register 54h. for each interrupt event in descending order of priority, check if the corresponding x i bit in 54h is ?1?. if yes, execute corresponding interrupt routine, then write ?0? to the x i bit. if no, continue to next lower priority interrupt. after all interrupts have been checked, check if the global interrupt is still asserted. if yes, repeat procedure. if no, jump back to process that ran before the interrupt.
WM9715L production data w pd rev 4.0 december 2007 54 power management the WM9715L includes the standard power down control register defined by the ac?97 specification (register 26h). additionally, it also allows more specific control over the individual blocks of the device through register 24h. each particular circuit block is active when both the relevant bit in register 26h and the relevant bit in register 24h are set to ?0?. default register address bit label normal pwrup pin ?hi? during reset description 14 pr6 0 (on) 1 (off) disables hpoutl, hpoutr and out3 buffer 13 pr5 0 (on) 1 (off) disables internal clock 12 pr4 0 (on) 1 (off) disables ac-link interface (external clock off) 11 pr3 0 (on) 1 (off) disables vref, analogue mixers and outputs 10 pr2 0 (on) 1 (off) disables analogue mixers, lout2, rout2 (but not vref) 9 pr1 0 (on) 1 (off) disables stereo dac 8 pr0 0 (on) 1 (off) disables audio adcs and input mux 3 ref 1 0 read-only bit, indicates vref is ready (inverse of pr2) 2 anl 1 0 read-only bit, indicates analogue mixers are ready (inverse of pr3) 1 dac 1 0 read-only bit, indicates audio dacs are ready (inverse of pr1) 26h powerdown/ status register 0 adc 1 0 read-only bit, indicates audio adcs are ready (inverse of pr0) table 39 powerdown and status register (conforms to ac?97 rev 2.2) power-up as can be seen from the table above, most blocks are ?on? by default. however, if the pwrup pin is held high during reset, the WM9715L starts up with all blocks powered down, saving power. this is achieved by connecting a pull-up resistor (e.g. 100k ? ) from pwrup to dbvdd. note that the state of pwrup during reset only affects register 26h.
production data WM9715L w pd rev 4.0 december 2007 55 table 40 extended power down register (additional to ac?97 rev 2.2) note: *when disabling a pga, always ensure that it is muted first. additional power management: ? auxdac: see ?auxiliary dac? section. auxdac is off by default. ? touchpanel interface: see ?controlling the touchpanel digitiser / power management?. the touchpanel digitiser is off by default. sleep mode whenever the pr4 bit (reg. 26h) is set, the ac-link interface is disabled, and the WM9715L is in sleep mode. there is in fact a very large number of different sleep modes, depending on the other control bits. for example, the low-power standby mode described below is a sleep mode. it is desirable to use sleep modes whenever possible, as this will save power. the following functions do not require a clock and can therefore operate in sleep mode: ? analogue-to-analogue audio (dacs and adcs unused), e.g. phone call mode ? pen-down detection ? interrupts ? battery alarm / analogue comparators (but not battery measurement) the WM9715L can awake from sleep mode as a result of ? a warm reset on the ac-link (according to the ac?97 specification) ? an interrupt event such as pen-down, battery alarm, etc (if interrupt wake-up is enabled ? see ?interrupt control? section) register address bit label default description 15 pd15 0 (on) disables crystal oscillator 14 pd14 0 (on) disables left audio dac 13 pd13 0 (on) disables right audio dac 12 pd12 0 (on) disables left audio adc 11 pd11 0 (on) disables right audio adc 10 pd10 0 (on) disables micbias 9 pd9 0 (on) disables left headphone mixer 8 pd8 0 (on) disables right headphone mixer 7 pd7 0 (on) disables speaker mixer 6 pd6 0 (on) disables mono_out buffer (pin 33) and phone mixer 5 pd5 0 (on) disables out3 buffer (pin 37) 4 pd4 0 (on) disables headphone buffers (hpoutl/r) 3 pd3 0 (on) disables speaker outputs (lout2, rout2) 2 pd2 0 (on) disables line input pga (left and right) * 1 pd1 0 (on) disables phone input pga * 24h additional power down control 0 pd0 0 (on) disables mic input pga (left and right) *
WM9715L production data w pd rev 4.0 december 2007 56 low power standby mode if all the bits in registers 26h and 24h are set, then the WM9715L is in low-power standby mode and consumes very little current. a 1m ? resistor string remains connected across avdd to generate vref. this is necessary if the on-chip analogue comparators are used (see ?battery alarm and battery measurement? section), and helps shorten the delay between wake-up and playback readiness. if vref is not required, the 1m ? resistor string can be disabled by setting the svd bit, reducing current consumption further. register address bit label default description 58h 10 svd 0 vref disable 0: vref enabled using 1m ? string (low-power standby mode) 1 : vref disabled, 1m ? string disconnected (off mode) table 41 disabling vref (for lowest possible power consumption) saving power at low supply voltages the analogue supplies to the WM9715L can run from 1.8v to 3.6v. by default, all analogue circuitry on the ic is optimized to run at 3.3v. this set-up is also good for all other supply voltages down to 1.8v. however, at lower voltages, it is possible to save power by reducing the internal bias currents used in the analogue circuitry. this is controlled as shown below. register address bit label default description 5ch 6:5 vbias 00 analogue bias optimization 11 : lowest bias current, optimized for 1.8v 10 : low bias current, optimized for 2.5v 01, 00 : default bias current, optimized for 3.3v table 42 analogue bias selection
production data WM9715L w pd rev 4.0 december 2007 57 unused analogue inputs and outputs when analogue inputs or outputs are disabled, they remain internally connected to vref (avdd/2) through a large resistor. this maintains the potential at that node and helps to eliminate pops when the pins are re-enabled. there are several exceptions to this. firstly, when vref itself is disabled (pr3 = 1 in register 26h), unused analogue pins are not held at avdd/2. additionally: ? the mic1 input is disconnected from vref if all of the following register settings are applied: pd0 = 1 in register 24h and pr0 = 1 in register 26h and ms = 00 in register 0eh and (recsl = 000 or recsr = 000 in register 1ah) ? the mic2 input is disconnected from vref if all of the following register settings are applied: pd0 = 1 in register 24h and pr0 = 1 in register 26h and ms = 10 in register 0eh and (recsl = 000 or recsr = 000 in register 1ah) ? the pcbeep i nput is disconnected from vref if pr2 = 1 in register 26h ? the pcbeep i nput is also disconnected from vref if the exact following register settings are applied: pd9 = 1 in register 24h or b2h = 1 in register 0ah and (pd8 = 1 in register 24h or b2h = 1 in register 0ah) and (pd7 = 1 in register 24h or b2s = 1 in register 0ah) and (pd6 = 1 in register 24h or b2p = 1 in register 0ah) for mic1 and mic2, pop issues can be circumvented by disconnecting the microphone inputs from the record selector (recsl = recsr = 001 in register 1ah) in sleep or standby modes. however, should it be necessary to maintain the vref potential at mic1, mic2 or pcbeep, this can be achieved by choosing any suitable register settings that are not identical to those shown above.
WM9715L production data w pd rev 4.0 december 2007 58 ac97 data and control interface interface protocol the WM9715Lhas a single ac?97 interface for both data transfer and control. the ac-link uses 5 wires: ? sdatain (pin 8) carries data from the WM9715L to the controller ? sdataout (pin 5) carries data from the controller to the WM9715L ? bitclk (pin 6) is a clock, normally generated by the WM9715L crystal oscillator and supplied to the controller. however, bitclk can also be passed to the WM9715L from an off-chip generator. ? sync is a synchronization signal generated by the controller and passed to the WM9715L ? resetb resets the WM9715L to its default state figure 16 ac-link interface (typical case with bitclk generated by the ac97 codec) the sdatain and sdataout signals each carry 13 time-division multiplexed data streams (slots 0 to 12). a complete sequence of slots 0 to 12 is referred to as an ac-link frame, and contains a total of 256 bits. the frame rate is 48khz. this makes it possible to simultaneously transmit and receive multiple data streams (e.g. audio, touchpanel, auxdac, control) at sample rates up to 48khz. detailed information can be found in the ac?97 (revision 2.2) specification, which can be obtained at http://www.intel.com/design/chipsets/audio/ note: sdataout and sync must be held low for when resetb is applied. these signals must be held low for the entire duration of the resetb pulse and especially during the low-to-high transition of resetb. if either is set high during reset the ac?97 device may enter test modes. information relating to this operation is available in the ac?97 specification or in wolfson applications note wan-0104 available at www.wolfsonmicro.com .
production data WM9715L w pd rev 4.0 december 2007 59 interface timing test characteristics: dbvdd = 3.3v, dcvdd = 3.3v, dgnd1 = dgnd2 = 0v, t a = -25 c to +85 c, unless otherwise stated. clock specifications bitclk sync t clk_high t clk_low t clk_period t sync_high t sync_low t sync_period figure 17 clock specifications (50pf external load) parameter symbol min typ max unit bitclk frequency 12.288 mhz bitclk period t clk_period 81.4 ns bitclk output jitter 750 ps bitclk high pulse width (note 1) t clk_high 36 40.7 45 ns bitclk low pulse width (note 1) t clk_low 36 40.7 45 ns sync frequency 48 khz sync period t sync_period 20.8 s sync high pulse width t sync_high 1.3 s sync low pulse width t sync_low 19.5 s note: 3 worst case duty cycle restricted to 45/55 data setup and hold figure 18 data setup and hold (50pf external load) note: setup and hold times for sdatain are with respect to the ac?97 controller, not the WM9715L. parameter symbol min typ max unit setup to falling edge of bitclk t setup 10 ns hold from falling edge of bitclk t hold 10 ns output valid delay from rising edge of bitclk t co 15 ns
WM9715L production data w pd rev 4.0 december 2007 60 signal rise and fall times bitclk sync sdatain sdataout t rise clk t fall clk t rise sync t fall sync t rise din t fall din t rise dout t fall dout figure 19 signal rise and fall times (50pf external load) parameter symbol min typ max unit incoming signals (from the ac?97 controller to the WM9715L) sdataout rise time trise dout 6 ns sdataout fall time tfall dout 6 ns sync rise time trise sync 6 ns sync fall time tfall sync 6 ns outgoing signals (from the WM9715L to the ac?97 controller) bitclk rise time trise clk 6 ns bitclk fall time tfall clk 6 ns sdatain rise time trise din 6 ns sdatain fall time tfall din 6 ns ac-link powerdown sync bitclk sdataout write to 0x20 data pr4 don't care sdatain slot 1 slot 2 t s2_pdown figure 20 ac-link powerdown timing ac-link powerdown occurs when pr4 (register 26h, bit 12) is set (see ?power management? section). parameter symbol min typ max unit end of slot 2 to bitclk and sdatain low t s2_pdown 1.0 s
production data WM9715L w pd rev 4.0 december 2007 61 cold reset (asynchronous, resets register settings) resetb bitclk t rst_low t rst2clk figure 21 cold reset timing note: for correct operation sdataout and sync must be held low for entire resetb active low period otherwise the device may enter test mode. see ac?97 specification or wolfson applications note wan104 for more details. parameter symbol min typ max unit resetb active low pulse width t rst_low 1.0 s resetb inactive to bitclk startup delay t rst2clk 162.8 ns warm reset (asynchronous, preserves register settings) figure 22 warm reset timing parameter symbol min typ max unit sync active high pulse width t sync_high 1.3 s sync inactive to bitclk startup delay t rst2clk 162.4 ns
WM9715L production data w pd rev 4.0 december 2007 62 register map note: highlighted bits differ from the ac?97 specification (newly added for non-ac?97 function, or same bit used in a different way, or for another function) reg name 1514131211109 8 7 6 543210default 00h reset 0 se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 6174h 02h lout2/rout2 volume mu 0 zc inv 8000h 04h headphone volume mu 0 zc 0 8000h 06h monoout volume mu 0 0 0 0 0 0 0 zc 0 0 8000h 08h dac tone control bb 0 0 bc 0 dat 0 tc 0f0fh 0ah pcbeep input b2h b2s b2p 0 0 0 0 aaa0h 0ch phone volume p2h p2s 0 0 0 0 0 0 0 0 0 c008h 0eh mic volume 0 m12p m22p 20db 6808h 10h linein volume l2h l2s l2p 0 0 0 e808h 12h auxdac volume / routing a2h a2s a2p 0 0 0 axe aaa0h 14h sidetone volume stm 0 000000ad00h 16h out3 volume mu 0 0 0 0 src zc 0 8000h 18h dac volume d2h d2s d2p 0 0 0 e808h 1ah record select 0 boost r2p bst 0 0 0 0 0 3000h 1ch record gain rmu grl zc grr 8000h 20h general purpose 0 0 3de 0 0 0 0 0 lb 0 0 0 0 0 0 0 0000h 22h dac 3d control 0 0 0 0 0 0 0 0 0 0 3dlc 3duc 0000h 24h powerdown pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 0000h 26h powerdown ctrl/stat 0 pr6 pr5 pr4 pr3 pr2 pr1 pr0 0 0 0 0 ref anl dac adc 000fh ff00h 28h extended audio id id1 id0 0 0 rev1 rev0 amap ldac sdac cdac 0 0 vrm spdif dra vra 0405h 2ah ext?d audio stst/ctrl 0 0 0 0 0 spcv 0 0 0 0 0 sen 0 vra 0410h 2ch audio dacs sample rate bb80h 2eh auxdac sample rate bb80h 32h audio adcs sample rate bb80h 3ah spdif control v drs l pre copy aud ib pro 2000h 4ch pin configurations (1) 1 1 1 1 1 0 0 0 0 0 gc5 gc4 gc3 gc2 1 0 f83eh 4eh interrupt polarity c1p c2p pp ap tp 1 1 1 1 1 1 1 1 1 1 1 ffffh 50h interrupt sticky c1s c2s ps as ts 0 0 0 0 0 0 0 0 0 0 0 0000h 52h interrupt wake-up c1w c2w pw aw tw 0 0 0 0 0 0 0 0 0 0 0 0000h 54h interrupt flags c1i c2i pi ai ti 0 0 0 0 0 0 0 0 0 gi1 0 interrupts 56h pin configurations (2) 1 1 1 1 1 0 0 0 0 0 ge5 ge4 ge3 ge2 1 0 f83eh 58h additional functions (1) 0 0 svd 0 0 0 0 0 0 wake en irq inv 0008h 5ah vendor reserved 5ch add. functions (2) amute c1 ref c2 ref ds amen adco hpf ent 0000h 5eh vendor reserved 60h alc control b032h 62h alc / noise gate control alc zc ng at 0 ngg 3e00h 64h auxdac input control xsle 0000h 66h- 74h vendor reserved 76h digitiser reg 1 poll coo ctc slen 0006h 78h digitiser reg 2 rpr 45w pden 0 wait pil 0 0 0001h 7ah digitiser read back pndn 0000h 7ch vendor id1 574dh 7eh vendor id2 4c12h adcsrc prp reserved for test maxgain zc timeout adcsel dcy (decay time) atk (attack time) c2src auxdacslt rpu del ass c1src vbias alcl (target level) hld (hold time) out3src a2pvol monoout volume bass trbl micvol (mono /right) ms b2pvol phonein volume lmicvol (left only) (extended) hpoutr volume hpoutl volume recsl recsr left dac volume right dac volume r2p alcm alcvol 3ddepth dacsr (audio dacs sample rate) auxdacsr (auxiliary dac sample rate) spsa default for reg. 26h - pin 47 "low" default for reg. 26h - pin 47 "high" during reset (recommended for lowest power) ascii character ?l? ?12? (indicates part family) ngth (threshold) auxdac val ascii character ?w? ascii character ?m? alcsel cr slt adcd (touchpanel adc data) b2hvol comp2del b2svol spsr cc (category code) adcsr (audio adcs sample rate) (extended) recvoll recvolr die revision reserved for test reserved. do not write to these registers out3 volume lout2 volume rout2 volume stvol lineinlvol lineinrvol a2hvol a2svol table 43 WM9715L register map
production data WM9715L w pd rev 4.0 december 2007 63 register bits by address register 00h is a read-only register. writing any value to this register resets all registers to their default, but does not change the contents of reg. 00h. reading the register reveals information about the codec to the driver, as required by the ac?97 specification, revision 2.2 reg addr bit label default description refer to 14:10 se [4:0] 11000 indicates a codec from wolfson microelectronics 9:6 id9:6 0101 indicates 18 bits resolution for adcs and dacs 5 id5 1 indicates that the WM9715L supports bass boost 4 id4 1 indicates that the WM9715L has a headphone output 3 id3 0 indicates that the WM9715L does not support simulated stereo 2 id2 1 indicates that the WM9715L supports bass and treble control 1 id1 0 indicates that the WM9715L does not support modem functions 00h 0 id0 0 indicates that the WM9715L does not have a dedicated microphone adc intel?s ac?97 component specification, revision 2.2, page 50 register 02h controls the output pins lout2 and rout2. reg addr bit label default description refer to 15 mu 1 (mute) mutes lout2 and rout2. 13:8 lout2 vol 000000 (0db) lout2 volume 7 zc 0 (off) enables zero-cross detector 6 inv 0 (not inverted) inverts lout2 (for btl speaker operation) 02h 5:0 rout2 vol 000000 (0db) rout2 volume analogue audio outputs register 04h controls the headphone output pins, hpoutl and hpoutr. reg addr bit label default description refer to 15 mu 1 (mute) mutes hpoutl and hpoutr. 13:8 hpoutl vol 000000 (0db) hpoutl volume 7 zc 0 (off) enables zero-cross detector 04h 5:0 hpoutr vol 000000 (0db) hpoutr volume analogue audio outputs register 06h controls the analogue output pin monoout. reg addr bit label default description refer to 15 mu 1 (mute) mutes monoout. 7 zc 0 (off) enables zero-cross detector 06h 5:0 monoout vol 000000 (0db) monoout volume analogue audio outputs
WM9715L production data w pd rev 4.0 december 2007 64 register 08h controls the bass and treble response of the left and right audio dac (but not auxdac). reg addr bit label default description refer to 15 bb 0 (linear) selects linear bass control or adaptive bass boost 12 bc 0 (low) selects bass cut-off frequency 11:8 bass 1111 (off) controls bass intensity 6 dat 0 (off) enables 6db pre-dac attenuation 4 tc 0 (high) selects treble cut-off frequency 08h 3:0 trbl 1111 (off) controls treble intensity audio dacs, tone control / bass boost register 0ah controls the analogue input pin pcbeep. reg addr bit label default description refer to 15 b2h 1 (mute) mutes pcbeep to headphone mixer path 14:12 b2hvol 010 (0db) controls gain of pc beep to headphone mixer path 11 b2s 1 (mute) mutes pcbeep to s peaker mixer path 10:8 b2svol 010 (0db) controls gain of pc beep to s peaker mixer path 7 b2p 1 (mute) mutes pcbeep to phone mixer path 0ah 6:4 b2pvol 010 (0db) controls gain of pc beep to phone mixer path analogue inputs, pcbeep i nput register 0ch controls the analogue input pin phone. reg addr bit label default description refer to 15 p2h 1 (mute) mutes phone to headphone mixer path 14 p2s 1 (mute) mutes phone to speaker mixer path 0ch 4:0 phonevol 01000 (0db) controls phone input gain to all mixers (but not to adc) analogue inputs, phone input register 0eh controls the analogue input pins mic1 and mic2. reg addr bit label default description refer to 14 m12p 1 (mute) mutes mic1 to phone mixer path 13 m22p 1 (mute) mutes mic2 to phone mixer path 12:8 lmicvol 01000 (0db) controls volume of mic1 (left), in stereo mode only 7 20db 0 (off) enables 20db gain boost 6:5 ms 00 (mic1 only) selects microphone mode. 00=mic1 only, 01=differential, 10=mic2 only, 11=stereo 0eh 4:0 micvol 01000 (0db) controls mic volume (except mic1 in stereo mode) analogue inputs, microphone input register 10h controls the analogue input pins lineinl and lineinr. reg addr bit label default description refer to 15 l2h 1 (mute) mutes linein to headphone mixer path 14 l2s 1 (mute) mutes linein to speaker mixer path 13 l2p 1 (mute) mutes linein to phone mixer path 12:8 lineinlvol 01000 (0db) controls lineinl input gain to all mixers (but not to adc) 10h 4:0 lineinrvol 01000 (0db) controls lineinr input gain to all mixers (but not to adc) analogue inputs, line input
production data WM9715L w pd rev 4.0 december 2007 65 register 12h controls the output signal of the auxiliary dac. reg addr bit label default description refer to 15 a2h 1 (mute) mutes auxdac to headphone mixer path 14:12 a2hvol 010 (0db) controls gain of auxdac to headphone mixer path 11 a2s 1 (mute) mutes auxdac to speaker mixer path 10:8 a2svol 010 (0db) controls gain of auxdac to speaker mixer path 7 a2p 1 (mute) mutes auxdac to phone mixer path 6:4 a2pvol 010 (0db) controls gain of auxdac to phone mixer path 12h 0 axe 0 (0ff) enables auxdac auxiliary dac register 14h controls the side tone paths. reg addr bit label default description refer to 15 stm 1 (mute) mutes microphone to headphone mixer path 14:12 stvol 010 (0db) controls gain of microphone to headphone mixer path 11:10 alcm 11 (mute both) selects alc to headphone mixer path. 00=stereo, 01=right only, 10=left only, 11=mute both left and right 14h 9:7 alcvol 010 (0db) controls gain of alc to headphone mixer path audio mixers, side tone control register 16h controls the analogue output pin out3, and also contains one control bit that affects lout2 and rout2. reg addr bit label default description refer to 15 mu 1 (mute) mutes out3. 10:9 out3src 00 (-hpoutr) selects source of out3 signal. 00=-hpoutr, 01=vref, 10=hpoutl+hpoutr, 11=-monoout 8 src 0 (spkr mix) selects source of lout2 and rout2 signals. 0=from speaker mixer, 1=from headphone mixer 7 zc 0 (disabled) zero-cross enable 16h 5:0 out3vol 000000 (0db) out3 volume analogue audio outputs register 18h controls the audio dacs (but not auxdac). reg addr bit label default description refer to 15 d2h 1 (mute) mutes dac to headphone mixer path 14 d2s 1 (mute) mutes dac to speaker mixer path 13 d2p 1 (mute) mutes dac to phone mixer path 12:8 ldacvol 01000 (0db) controls left dac input gain to all mixers 18h 4:0 rdacvol 01000 (0db) controls right dac input gain to all mixers audio dacs register 1ah controls the record selector and the adc to phone mixer path. reg addr bit label default description refer to 14 boost 0 (off) enables 20db gain boost for recording 13:12 r2p 11 (mute) controls adc to phone mixer path. 00=stereo, 01=left adc only, 10=right adc only, 11=mute left and right 11 r2pbst 0 (off) enables 20db gain boost for adc to phone mixer path 10:8 recsl 000 (mic) selects left adc signal source 1ah 2:0 recsr 000 (mic) selects right adc signal source audio adc, record selector
WM9715L production data w pd rev 4.0 december 2007 66 register 1ch controls the.recording gain. reg addr bit label default description refer to 15 rmu 1 (mute) mutes audio adc input 14 grl 0 (standard) selects gain range for pga of left adc. 0=0...+22.5db in 1.5db steps, 1=-17.25...+30db in 0.75db steps 13:8 recvoll 000000 (0db) controls left adc recording volume 7 zc 0 (off) enables zero-cross detector 6 grr 0 (standard) selects gain range for pga of left adc. 0=0...+22.5db in 1.5db steps, 1=-17.25...+30db in 0.75db steps 1ch 5:0 recvolr 000000 (0db) controls right adc recording volume audio adc, record gain register 20h is a ?general purpose? register as defined by the ac?97 specification. only two bits are implemented in the WM9715L. reg addr bit label default description refer to 13 3de 0 (off) enables 3d enhancement audio dacs, 3d stereo enhancement 20h 7 lb 0 (off) enables loopback (i.e. feed adc output data directly into dac) intel?s ac?97 component specification, revision 2.2, page 55 register 22h controls 3d stereo enhancement for the audio dacs. reg addr bit label default description refer to 5 3dlc 0 (low) selects lower cut-off frequency 4 3duc 0 (high) selects upper cut-off frequency 22h 3:0 3ddepth 0000 (0%) controls depth of 3d effect audio dacs, 3d stereo enhancement register 24h is for power management additional to the ac?97 specification. note that the actual state of each circuit block depends on both register 24h and register 26h. reg addr bit label default description refer to 15 pd15 0 * disables crystal oscillator 14 pd14 0 * disables left audio dac 13 pd13 0 * disables right audio dac 12 pd12 0 * disables left audio adc 11 pd11 0 * disables right audio adc 10 pd10 0 * disables micbias 9 pd9 0 * disables left headphone mixer 8 pd8 0 * disables right headphone mixer 7 pd7 0 * disables speaker mixer 6 pd6 0 * disables mono_out buffer (pin 33) and phone mixer 5 pd5 0 * disables out3 buffer (pin 37) 4 pd4 0 * disables headphone buffers (hpoutl/r) 3 pd3 0 * disables speaker outputs (lout2, rout2) 2 pd2 0 * disables line input pga (left and right) 1 pd1 0 * disables phone input pga 24h 0 pd0 0 * disables mic input pga (left and right) power management * ?0? corresponds to ?on?, if and only if the corresponding bit in register 26h is also 0.
production data WM9715L w pd rev 4.0 december 2007 67 register 26h is for power management according to the ac?97 specification. note that the actual state of many circuit blocks depends on both register 24h and register 26h. reg addr bit label default description refer to 14 pr6 disables hpoutl, hpoutr and out3 buffer 13 pr5 disables internal clock 12 pr4 disables ac-link interface (external clock off) 11 pr3 disables vref, analogue mixers and outputs 10 pr2 disables analogue mixers, lout2, rout2 (but not vref) 9 pr1 disables stereo dac and auxdac 8 pr0 see note disables audio adcs and input mux 3 ref inverse of pr2 read-only bit, indicates vref is ready 2 anl inverse of pr3 read-only bit, indicates analogue mixers are ready 1 dac inverse of pr1 read-only bit, indicates audio dacs are ready 0 adc inverse of pr0 read-only bit, indicates audio adcs are ready power management note: pr6 to pr0 default to 1 if the pwrup pin is held high during reset, otherwise they default to 0. register 28h is a read-only register that indicates to the driver which advanced ac?97 features the WM9715L supports. reg addr bit label default description refer to 15:14 id 00 indicates that the WM9715L is configured as the primary codec in the system. 11:10 rev 01 indicates that the WM9715L conforms to ac?97 rev2.2 9 amap 0 indicates that the WM9715L does not support slot mapping 8 ldac 0 indicates that the WM9715L does not have an lfe dac 7 sdac 0 indicates that the WM9715L does not have surround dacs 6 cdac 0 indicates that the WM9715L does not have a centre dac 3 vrm 0 indicates that the WM9715L does not have a dedicated, variable rate microphone adc 2 spdif 1 indicates that the WM9715L supports spdif output 1 dra 0 indicates that the WM9715L does not support double rate audio 28h 0 vra 1 indicates that the WM9715L supports variable rate audio intel?s ac?97 component specification, revision 2.2, page 59 register 2ah controls the spdif output and variable rate audio. reg addr bit label default description refer to 10 spcv 1 (valid) spdif validity bit (read-only) 5:4 spsa 01 (slots 6, 9) controls spdif slot assignment. 00=slots 3 and 4, 01=6/9, 10=7/8, 11=10/11 2 sen 0 (off) enables spdif_out pin (note that gc5 in register 4ch and ge5 in register 56h must also be set to 0) 2ah 0 vra 0 (off) enables variable rate audio digital audio (spdif) output registers 2ch, 2eh 32h and control the sample rates for the stereo dac, auxiliary dac and audio adc, respectively. reg addr bit label default description refer to 2ch all dacsr bb80h controls stereo dac sample rate 2eh all auxdacsr bb80h controls auxiliary dac sample rate 32h all adcsr bb80h controls audio adc sample rate variable rate audio / sample rate conversion note: the vra bit in register 2ah must be set first to obtain sample rates other than 48khz
WM9715L production data w pd rev 4.0 december 2007 68 register 3ah controls the spdif output. reg addr bit label default description refer to 15 v 0 validity bit; ?0? indicates frame valid, ?1? indicates frame not valid 14 drs 0 indicates that the WM9715L does not support double rate spdif output (read-only) 13:12 spsr 10 indicates that the wm 9715l only supports 48khz sampling on the spdif output (read-only) 11 l 0 generation level; programmed as required by user 10:4 cc 0000000 category code; programmed as required by user 3 pre 0 pre-emphasis; ?0? indicates no pre-emphasis, ?1? indicates 50/15us pre-emphasis 2 copy 0 copyright; ?0? indicates copyright is not asserted, ?1? indicates copyright 1 audib 0 non-audio; ?0? indicates data is pcm, ?1? indicates non- pcm format (e.g. dd or dts) 3ah 0 pro 0 professional; ?0? indicates consumer, ?1? indicates professional digital audio (spdif) output register 4ch (together with register 56h) controls the outputs adcirq, pendown, genirq and spdif_out. reg addr bit label default description refer to 5 gc5 1 (off) ?0? enables the spdif_out pin (note that ge5 in register 56h must also be set to 0, and sen in register 2ah to 1) 4 gc4 1 (off) ?0? enables the adcirq pin (note that ge4 in register 4ch must also be set to 0). 3 gc3 1 (off) ?0? enables the pendown pin (note that ge3 in register 4ch must also be set to 0). 4ch 2 gc2 1 (off) ?0? enables the genirq pin (note that ge2 in register 4ch must also be set to 0). interrupt control register 4eh to 54h control the processing of genirq interrupt signals. reg addr bit label default description refer to 4eh all 1 controls interrupt polarity 50h all 0 (not sticky) makes interrupt bits sticky 52h all 0 (off) enables wake-up for each interrupt 54h = status of internal interrupt signal interrupt status (read from inputs, write ?0? to clear sticky bits) 15 controls comparator 1 interrupts 14 controls comparator 2 interrupts 13 controls pen-down interrupts 12 controls auxadc data available interrupts 11 please refer to the register map controls thermal sensor interrupts interrupt control
production data WM9715L w pd rev 4.0 december 2007 69 register 56h (together with register 4ch) controls the outputs adcirq, pendown, genirq and spdif_out. reg addr bit label default description refer to 5 ge5 1 (off) ?0? enables the spdif_out pin (note that gc5 in register 4ch must also be set to 0, and sen in register 2ah to 1) 4 ge4 1 (off) ?0? enables the adcirq pin (note that gc4 in register 4ch must also be set to 0). 3 ge3 1 (off) ?0? enables the pendown pin (note that gc3 in register 4ch must also be set to 0). 56h 2 ge2 1 (off) ?0? enables the genirq pin (note that bit gc2 in register 4ch must also be set to 0). interrupt control register 58h controls several additional functions. reg addr bit label default description refer to 15:13 comp2del 000 (no delay) selects comparator 2 delay battery alarm 10 svd 0 (enabled) disables vref for lowest possible power consumption power management 3:2 die rev indicates device revision. 00=rev.a, 01=rev.b, 10=rev.c n/a 1 wakeen 0 (no wake-up) e nables genirq interrupt wake-up 58h 0 irq inv 0 (not inverted) inverts the genirq signal (pin 45) interrupt control register 5ch controls several additional functions. reg addr bit label default description refer to 15 amute 0 read-only bit to indicate dac auto-muting audio dacs, stereo dacs 14 c1ref 0 (avdd/2) selects comparator 1 reference voltage 13:12 c1src 00 (off) selects comparator 1 signal source 11 c2ref 0 (avdd/2) selects comparator 1 reference voltage 10:9 c2src 00 (off) selects comparator 1 signal source battery alarm 8 ds 0 selects differential microphone input pins. 0=mic1 and mic2, 1=linel and liner analogue inputs, microphone input 7 amen 0 (off) enables dac auto-mute 6:5 vbias 00 selects analogue bias for lowest power, depending on avdd supply. 0x=3.3v, 10=2.5v, 11=1.8v power management 4 adco 0 selects source of spdif data. 0=from sdataout, 1= from audio adc digital audio (spdif) output 3 hpf 0 disables adc high-pass filter audio adc 2 ent 0 enables thermal sensor analogue audio outputs, thermal sensor 5ch 1:0 ass 00 selects time slots for stereo adc data. 00=slots 3 and 4, 01=7/8, 10=6/9, 11=10/11 audio adc, adc slot mapping
WM9715L production data w pd rev 4.0 december 2007 70 registers 60h and 62h control the alc and noise gate functions. reg addr bit label default description refer to 15:12 alcl 1011 (-12db) controls alc threshold 11:8 hld 0000 (0 ms) controls alc hold time 7:4 dcy 0011 (192 ms) controls alc decay time 60h 3:0 atk 0010 (24 ms) controls alc attack time 15:14 alcsel 00 (off) controls which channel alc operates on. 00=none, 01=right only, 10=left only, 11=both 13:11 maxgain 111 (+30db) controls upper gain limit for alc 10:9 zc timeout 11 (slowest) controls time-out for zero-cross detection 8 alczc 0 (off) enables zero-cross detection for alc 7 ngat 0 (off) enables noise gate function 5 ngg 0 (hold gain) selects noise gate type. 0=hold gain, 1=mute 62h 4:0 ngth 00000 (-76.5db) controls noise gate threshold audio adc, automatic level control register 64h controls the input signal of the auxiliary dac. reg addr bit label default description refer to 15 xsle 0 selects input for auxdac. 0=from auxdacval (for dc signals), 1=from ac-link slot (for ac signals) 14:12 auxdacslt 000 (slot 5) selects input slot for auxdac (with xsle=1) 64h 11:0 auxdacval 000000000 auxdac digital input for auxdac (with xsle=0). 000h= minimum, fffh=full-scale auxiliary dac registers 76h, 78h and 7ah control the touchpanel interface. reg addr bit label default description refer to 15 poll 0 writing ?1? starts a measurement (this bit resets itself) 14:12 adcsel 000 (none) selects measurement type 11 coo 0 (off) enables co-ordinate mode 10 ctc 0 (polling) enables continuous conversions 9:8 cr 00 (93.75hz) controls conversion rate in continuous mode 7:4 del 0000 (20.8 s) controls touchpanel settling time 3 slen 1 enables slot readback of touchpanel data 76h 2:0 slt 10 selects time slot for readback of touchpanel data 15:14 prp 00 selects mode of operation. 00=off, 01=pen detect with wake-up, 10=pen detect without wake-up, 11=running 13 rpr 0 selects wake-up mode. 0=ac-link only, 1=ac-link and WM9715L auto-wake-up 12 45w 0 (4-wire) selects 4-wire or 5-wire touchpanel 11 pden 0 (always) selects when touchpanel measurements take place. 0=always, 1=only when pen is down 9 wait 0 controls data readback from register 7ah. 0=overwrite old data with new, 1=wait until old data has been read 8 pil 0 (200 a) controls current used for pressure measurement. 1=400 a 78h 5:0 rpu 000001 (68k ? ) controls internal pull-up resistor for pen-down detection 15 pndn 0 (pen up) indicates pen status. 14:12 adcsrc 000 (none) indicates measurement type 7ah read only 11:0 adcd 000h returns data from touchpanel / auxadc touchpanel interface
production data WM9715L w pd rev 4.0 december 2007 71 register 7ch and 7eh are read-only registers that indicate the device family to the driver. reg addr bit label default description refer to 15:8 f7:0 57h ascii character ?w? for wolfson 7ch 7:0 s7:0 4dh ascii character ?m? 15:8 t7:0 4ch ascii character ?l? 7eh 7:0 rev7:0 12h part family identifier intel?s ac?97 component specification, revision 2.2, page 50
WM9715L production data w pd rev 4.0 december 2007 72 applications information recommended external components figure 23 external components diagram
production data WM9715L w pd rev 4.0 december 2007 73 recommended components values component reference suggested value description c1 ? c6 100nf de-coupling for dbvdd,dcvdd,tpvdd,avdd, spkvdd,hpvdd c7 ? c8 10uf reservoir capacitor for dvdd, avdd. should the supplies use separate sources then additional capacitors will be required of each additional source. c9 100nf de-coupling for cap2. c10 10uf reservoir capacitor for cap2 c11 100nf de-coupling for vref c12 10uf reservoir capacitor for vref c13 100nf de-coupling for micbias ? not required if micbias output is not used c14 10uf reservoir capacitor for micbias ? not required if micbias output is not used c27 & c28 22pf required when used with a parallel resonant crystal. c15 ? c20 1uf ac coupling capacitors c21 ? c23 2.2uf output ac coupling capacitors to remove vref dc level from outputs c24 ? c26 220 f output ac coupling capacitors to remove vref dc level from outputs. r1 100k ? pull-up resistor, ensures that all circuit blocks are off by default xt 24.576mhz ac?97 master clock frequency. a bias resistor is not required but if connected will not affect operation if the value is large (above 1m ? ) table 44 external components descriptions note: 3 for capacitors c7, c8, c10, c12 and c14 it is recommended that very low esr components are used. line output the headphone outputs, hpoutl and hpoutr, can be used as stereo line outputs. the speaker outputs, lout2 and rout2, can also be used as line outputs, if lout2 is not inverted for btl operation (inv = 0). recommended external components are shown below. figure 24 recommended circuit for line output the dc blocking capacitors and the load resistance together determine the lower cut-off frequency, fc. assuming a 10 k ? load and c1, c2 = 10 f: fc = 1 / 2 (r l +r 1 ) c 1 = 1 / (2 x 10.1k ? x 1 f) = 16 hz increasing the capacitance lowers fc, improving the bass response. smaller values of c1 and c2 will diminish the bass response. the function of r1 and r2 is to protect the line outputs from damage when used improperly.
WM9715L production data w pd rev 4.0 december 2007 74 ac-coupled headphone output the circuit diagram below shows how to connect a stereo headphone to the WM9715L. figure 25 simple headphone output circuit diagram the dc blocking capacitors c1 and c2 together with the load resistance determine the lower cut-off frequency, fc. increasing the capacitance lowers fc, improving the bass response. smaller capacitance values will diminish the bass response. for example, with a 16 ? load and c1 = 220 f: fc = 1 / 2 r l c 1 = 1 / (2 x 16 ? x 220 f) = 45 hz dc coupled (capless) headphone output in the interest of saving board space and cost, it may be desirable to eliminate the 220 f dc blocking capacitors. this can be achieved by using out3 as a headphone pseudo-ground, as shown below. figure 26 capless headphone output circuit diagram (out3src = 10) as the out3 pin produces a dc voltage of avdd/2, there is no dc offset between hpoutl/hpoutr and out3, and therefore no dc blocking capacitors are required. however, this configuration has some drawbacks: ? the power consumption of the WM9715L is increased, due to the additional power consumed in the out3 output buffer. ? if the dc coupled output is connected to the line-in of a grounded piece of equipment, then out3 becomes short-circuited. although the built-in short circuit protection will prevent any damage to the WM9715L, the audio signal will not be transmitted properly. ? out3 cannot be used for another purpose
production data WM9715L w pd rev 4.0 december 2007 75 btl loudspeaker output lout2 and rout2 can differentially drive a mono 8 ? loudspeaker as shown below. figure 27 speaker output connection (inv = 1) the right channel is inverted by setting the inv bit, so that the signal across the loudspeaker is the sum of left and right channels. combined stereo headset / btl ear speaker in smartphone applications with a loudspeaker and separate ear speaker (receiver), a btl ear speaker can be connected at the out3 pin, as shown below. figure 28 combined headset / btl ear speaker (out3src = 00) the ear speaker and the stereo headset play the same signal. whenever the headset is plugged in, the headphone outputs are enabled and out3 disabled. when the headset is not plugged in, out3 is enabled. this requires the use of a headset jack with a built-in mechanical switch, connected to a gpio pin on the system cpu. depending on the state of the switch, the gpio pin is either grounded or high (due to a pull-up resistor). whenever the cpu detects a change in the gpio logic level, it should update the WM9715L registers to enable / disable the appropriate analogue outputs. combined headset / single-ended ear speaker instead of a btl ear speaker, a single-ended ear speaker can also be used, as shown below. figure 29 combined headset / single-ended ear speaker (out3src = 01)
WM9715L production data w pd rev 4.0 december 2007 76 package dimensions e dm029.e fl: 48 pin qfn plastic package 7 x 7 x 0.9 mm body, 0.50 mm lead pitch index area (d/2 x e/2) top view c aaa 2 x see detail 2 e2 e2/2 b d2 24 l d2/2 c aaa 2 x 25 36 37 48 1 12 13 d e e datum see detail 1 c 0.08 c ccc a a1 c (a3) seating plane detail 3 detail 3 detail 2 terminal tip r e/2 1 detail 1 (a3) g t h w b exposed lead half etch tie bar symbols dimensions (mm) min nom max note a b d d2 e e2 e l 0.80 0.90 1.00 0.30 0.25 0.18 7.00 bsc 5.25 5.15 5.00 7.00 bsc 0.5 bsc 5.15 5.25 5.00 0.30 0.4 0.50 1 a1 a3 0 0.02 0.05 0.20 ref g h 0.213 0.1 notes: 1. dimension b applied to metallized terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. 2. all dimensions are in millimetres 3. the terminal #1 identifier and terminal numberi ng convention shall conf orm to jesd 95-1 spp-002. 4. coplanarity applies to the exposed heat sink slug as well as the terminals. 5. this drawing is subject to change without notice. 6. refer to application note wan _0118 for f urther information regarding pcb f ootprints and qfn package soldering. jedec, mo-220, variation vkkd-2 tolerances of form and position t w aaa bbb ccc 0.1 0.2 0.15 0.10 0.10 ref exposed ground paddle 6 r = 0.3mm exposed ground paddle bottom view side view
production data WM9715L w pd rev 4.0 december 2007 77 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at the date of shipment. wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. in order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. wolfson is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address: wolfson microelectronics plc 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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